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ldih/l
author
Stefan REBERNIG
<c0726283@ti18.(none)>
Tue, 21 Dec 2010 14:19:01 +0000
(15:19 +0100)
committer
Stefan REBERNIG
<c0726283@ti18.(none)>
Tue, 21 Dec 2010 14:19:01 +0000
(15:19 +0100)
cpu/src/alu_b.vhd
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cpu/src/common_pkg.vhd
patch
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cpu/src/core_top.vhd
patch
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cpu/src/decoder_b.vhd
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cpu/src/fetch_stage_b.vhd
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dt/dt.qsf
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diff --git
a/cpu/src/alu_b.vhd
b/cpu/src/alu_b.vhd
index e19b52dfd544cbdb0a4eb4b5d0f9036ff3fbb4b9..a7374face2fa6497cad465f36a972af0acf01fcf 100755
(executable)
--- a/
cpu/src/alu_b.vhd
+++ b/
cpu/src/alu_b.vhd
@@
-132,7
+132,18
@@
begin
--right_o <= displacement;
addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));
if op_detail(IMM_OPT) = '1' then
--right_o <= displacement;
addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));
if op_detail(IMM_OPT) = '1' then
- result_v.result := right_operand;
+
+ result_v.result := right_operand;
+
+ if (op_detail(LDI_REPLACE_OPT) = '0') then
+ result_v.result := left_operand;
+ if (op_detail(LOW_HIGH_OPT) = '1') then
+ result_v.result(31 downto 16) := right_operand(31 downto 16);
+ else
+ result_v.result(15 downto 0) := right_operand(15 downto 0);
+ end if;
+ end if;
+
res_prod := '1';
mem_op := '0';
addr(DATA_ADDR_WIDTH + 2) <= '0';
res_prod := '1';
mem_op := '0';
addr(DATA_ADDR_WIDTH + 2) <= '0';
diff --git
a/cpu/src/common_pkg.vhd
b/cpu/src/common_pkg.vhd
index ca312f0b3040165deca10896e5101648c898dc54..43603d29a9638626502ee2c9640678e2f3ed711c 100755
(executable)
--- a/
cpu/src/common_pkg.vhd
+++ b/
cpu/src/common_pkg.vhd
@@
-55,9
+55,11
@@
package common_pkg is
constant ARITH_OPT : integer := 1;
constant HWORD_OPT : integer := 1;
constant PUSH_OPT : integer := 1;
constant ARITH_OPT : integer := 1;
constant HWORD_OPT : integer := 1;
constant PUSH_OPT : integer := 1;
+ constant LOW_HIGH_OPT : integer := 1;
constant CARRY_OPT : integer := 2;
constant BYTE_OPT : integer := 2;
constant CARRY_OPT : integer := 2;
constant BYTE_OPT : integer := 2;
+ constant LDI_REPLACE_OPT : integer := 2;
constant RIGHT_OPT : integer := 3;
constant JMP_REG_OPT : integer := 3;
constant RIGHT_OPT : integer := 3;
constant JMP_REG_OPT : integer := 3;
diff --git
a/cpu/src/core_top.vhd
b/cpu/src/core_top.vhd
index 730f6ce7af51d6670b9105f823ac83f2b472a177..14c04c382aa483d59ed24908373b27496eb8f95b 100644
(file)
--- a/
cpu/src/core_top.vhd
+++ b/
cpu/src/core_top.vhd
@@
-10,7
+10,7
@@
entity core_top is
port(
--System input pins
port(
--System input pins
- sys_res : in std_logic;
+ sys_res
_unsync
: in std_logic;
sys_clk : in std_logic;
-- result : out gp_register_t;
-- reg_wr_data : out gp_register_t
sys_clk : in std_logic;
-- result : out gp_register_t;
-- reg_wr_data : out gp_register_t
@@
-28,6
+28,9
@@
end core_top;
architecture behav of core_top is
architecture behav of core_top is
+ constant SYNC_STAGES : integer := 2;
+ constant RESET_VALUE : std_logic := '0';
+
signal jump_result : instruction_addr_t;
signal jump_result_pin : instruction_addr_t;
signal prediction_result_pin : instruction_addr_t;
signal jump_result : instruction_addr_t;
signal jump_result_pin : instruction_addr_t;
signal prediction_result_pin : instruction_addr_t;
@@
-59,9
+62,12
@@
architecture behav of core_top is
signal gpm_in_pin : extmod_rec;
signal gpm_out_pin : gp_register_t;
signal nop_pin : std_logic;
signal gpm_in_pin : extmod_rec;
signal gpm_out_pin : gp_register_t;
signal nop_pin : std_logic;
+
+ signal sys_res : std_logic;
signal vers, vers_nxt : exec2wb_rec;
signal vers, vers_nxt : exec2wb_rec;
+ signal sync : std_logic_vector(1 to SYNC_STAGES);
begin
fetch_st : fetch_stage
begin
fetch_st : fetch_stage
@@
-162,12
+168,20
@@
begin
vers.dmem_write_en <= '0';
vers.hword <= '0';
vers.byte_s <= '0';
vers.dmem_write_en <= '0';
vers.hword <= '0';
vers.byte_s <= '0';
+ sync <= (others => '0');
elsif rising_edge(sys_clk) then
vers <= vers_nxt;
elsif rising_edge(sys_clk) then
vers <= vers_nxt;
+
+ sync(1) <= sys_res_unsync xor RESET_VALUE;
+ for i in 2 to SYNC_STAGES loop
+ sync(i) <= sync(i - 1);
+ end loop;
+
end if;
end process;
end if;
end process;
+sys_res <= sync(SYNC_STAGES);
--init : process(all)
--init : process(all)
diff --git
a/cpu/src/decoder_b.vhd
b/cpu/src/decoder_b.vhd
index 41d02938f0b0529569ab0d2dbd63deeea6256ba8..d0a5070207a2c6004afad4717dd816e45fba0ba1 100644
(file)
--- a/
cpu/src/decoder_b.vhd
+++ b/
cpu/src/decoder_b.vhd
@@
-227,15
+227,16
@@
begin
end if;
if (instr_s.opcode = "11010") then --ldi
end if;
if (instr_s.opcode = "11010") then --ldi
+ instr_s.reg_src1_addr := instr_s.reg_dest_addr;
+ instr_s.op_detail(LOW_HIGH_OPT) := instr_s.high_low;
+ instr_s.op_detail(LDI_REPLACE_OPT) := instr_s.signext;
+
if (instr_s.high_low = '1') then
instr_s.immediate(31 downto 16) := instruction(18 downto 3);
instr_s.immediate(15 downto 0) := (others => '0');
else
instr_s.immediate(15 downto 0) := instruction(18 downto 3);
instr_s.immediate(31 downto 16) := (others => '0');
if (instr_s.high_low = '1') then
instr_s.immediate(31 downto 16) := instruction(18 downto 3);
instr_s.immediate(15 downto 0) := (others => '0');
else
instr_s.immediate(15 downto 0) := instruction(18 downto 3);
instr_s.immediate(31 downto 16) := (others => '0');
-
- --instr_s.immediate(11 downto 0) := instruction(14 downto 3);
- --instr_s.immediate(WORD_WIDTH-1 downto 12) := (others => '0');
end if;
if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then
end if;
if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then
diff --git
a/cpu/src/fetch_stage_b.vhd
b/cpu/src/fetch_stage_b.vhd
index e1faf1fd819cd8680904b1a097bfd217e61250e0..5a3f7556519938a35505fe158adb0e2d178b8fc0 100644
(file)
--- a/
cpu/src/fetch_stage_b.vhd
+++ b/
cpu/src/fetch_stage_b.vhd
@@
-17,7
+17,7
@@
signal instr_rd_data : instruction_word_t;
begin
begin
- instruction_ram : r_w_ram --rom
+ instruction_ram : r
om --r
_w_ram --rom
generic map (
PHYS_INSTR_ADDR_WIDTH,
WORD_WIDTH
generic map (
PHYS_INSTR_ADDR_WIDTH,
WORD_WIDTH
diff --git
a/dt/dt.qsf
b/dt/dt.qsf
index 02febd582589059a0b7bb414b1e314fd5a80dd15..1a461c3c0af95d206ecd4ba536d1f1b25f5218a4 100644
(file)
--- a/
dt/dt.qsf
+++ b/
dt/dt.qsf
@@
-55,8
+55,7
@@
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_location_assignment PIN_42 -to sys_res
-set_location_assignment PIN_166 -to bus_tx
+set_location_assignment PIN_178 -to bus_tx
set_location_assignment PIN_152 -to sys_clk
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_152 -to sys_clk
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
@@
-121,4
+120,6
@@
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_location_assignment PIN_153 -to bus_rx
+set_location_assignment PIN_42 -to sys_res_unsync
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file