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pipe v1
author
Stefan Rebernig
<stefan.rebernig@gmail.com>
Mon, 15 Nov 2010 17:32:14 +0000
(18:32 +0100)
committer
Stefan Rebernig
<stefan.rebernig@gmail.com>
Mon, 15 Nov 2010 17:32:14 +0000
(18:32 +0100)
cpu/sim/testcore.do
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cpu/src/alu_b.vhd
patch
|
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|
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cpu/src/exec_op/add_op_b.vhd
patch
|
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cpu/src/r2_w_ram_b.vhd
patch
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cpu/src/r_w_ram_b.vhd
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diff --git
a/cpu/sim/testcore.do
b/cpu/sim/testcore.do
index 6f5b7c880a0a78a5ce5892f088e2a64011c463c4..4f66a620be59e72dfc487b4582785ba444c55340 100644
(file)
--- a/
cpu/sim/testcore.do
+++ b/
cpu/sim/testcore.do
@@
-60,4
+60,4
@@
add wave -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
add wave -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
add wave -radix hexadecimal /pipeline_tb/decode_st/reg_we
add wave -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
add wave -radix hexadecimal /pipeline_tb/decode_st/reg_we
-run 5000
00
ns
+run 5000 ns
diff --git
a/cpu/src/alu_b.vhd
b/cpu/src/alu_b.vhd
index 3fb3434827af3647c95b48f6a2770de187f20901..f3a25ee836032a96a0114b9a460a06d03d09a353 100755
(executable)
--- a/
cpu/src/alu_b.vhd
+++ b/
cpu/src/alu_b.vhd
@@
-38,7
+38,7
@@
begin
shift_inst : exec_op
\r
port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);
\r
\r
shift_inst : exec_op
\r
port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);
\r
\r
-calc: process(cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)
\r
+calc: process(
left_operand, right_operand,
cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)
\r
variable result_v : alu_result_rec;
\r
variable res_prod : std_logic;
\r
variable cond_met : std_logic;
\r
variable result_v : alu_result_rec;
\r
variable res_prod : std_logic;
\r
variable cond_met : std_logic;
\r
@@
-48,7
+48,7
@@
begin
\r
result_v.result := add_result.result;
\r
res_prod := '1';
\r
\r
result_v.result := add_result.result;
\r
res_prod := '1';
\r
- mem_en := '0';
+ mem_en := '0';
\r
addr <= add_result.result;
\r
\r
case cond is
\r
addr <= add_result.result;
\r
\r
case cond is
\r
@@
-83,7
+83,7
@@
begin
when COND_ALWAYS =>
\r
cond_met := '1';
\r
when COND_NEVER =>
\r
when COND_ALWAYS =>
\r
cond_met := '1';
\r
when COND_NEVER =>
\r
- cond_met := '0';
+ cond_met := '0';
\r
when others => null;
\r
end case;
\r
\r
when others => null;
\r
end case;
\r
\r
@@
-111,8
+111,8
@@
begin
end if;
\r
\r
result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;
\r
end if;
\r
\r
result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;
\r
- result_v.mem_en := mem_en and cond_met;
-
+ result_v.mem_en := mem_en and cond_met;
\r
+
\r
\r
data <= add_result.result;
\r
alu_result <= result_v;
\r
\r
data <= add_result.result;
\r
alu_result <= result_v;
\r
diff --git
a/cpu/src/exec_op/add_op_b.vhd
b/cpu/src/exec_op/add_op_b.vhd
index 88e34d432b75e0ba2cf046959ef60f3e8e7a1e67..0e28af8af56b68303baa28adb1eb9bda4f1e0508 100644
(file)
--- a/
cpu/src/exec_op/add_op_b.vhd
+++ b/
cpu/src/exec_op/add_op_b.vhd
@@
-30,7
+30,8
@@
begin
complement := inc(not(right_operand));
l_neg := left_operand(gp_register_t'high);
complement := inc(not(right_operand));
l_neg := left_operand(gp_register_t'high);
- carry_res := unsigned('0' & left_operand)+addcarry;
+ --carry_res := unsigned('0' & left_operand)+addcarry;
+ carry_res := unsigned('0' & left_operand);
oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high));
if sub = '1' then
oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high));
if sub = '1' then
diff --git
a/cpu/src/r2_w_ram_b.vhd
b/cpu/src/r2_w_ram_b.vhd
index 3c71ade0c41a6d254832c95865d877cf64f11b35..d067ad3a9589ec053ac9a67edb6e52bec2da58fe 100644
(file)
--- a/
cpu/src/r2_w_ram_b.vhd
+++ b/
cpu/src/r2_w_ram_b.vhd
@@
-11,10
+11,10
@@
architecture behaviour of r2_w_ram is
type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
signal ram : RAM_TYPE := (
type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
signal ram : RAM_TYPE := (
- 0 => x"000000
1
0",
- 1 => x"00
110010
",
- 2 => x"000000
FF
",
- 3 => x"00
AB00BA
",
+ 0 => x"000000
0
0",
+ 1 => x"00
000001
",
+ 2 => x"000000
02
",
+ 3 => x"00
000003
",
others=> x"00000000");
begin
others=> x"00000000");
begin
diff --git
a/cpu/src/r_w_ram_b.vhd
b/cpu/src/r_w_ram_b.vhd
index f03388593c6ec05dddd76dd1604e820f0a3641f7..c9de81aab4d9d41194836885abee7ac44d67ccdb 100644
(file)
--- a/
cpu/src/r_w_ram_b.vhd
+++ b/
cpu/src/r_w_ram_b.vhd
@@
-11,7
+11,7
@@
architecture behaviour of r_w_ram is
type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000",
type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000",
- 1 => "111
0
0000000000001001000000000000",
+ 1 => "111
1
0000000000001001000000000000",
2 => "11100000000010001001000000000000",
3 => "11100001000110010111011001101100",
others => x"00000000");
2 => "11100000000010001001000000000000",
3 => "11100001000110010111011001101100",
others => x"00000000");