3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
8 architecture behaviour of r_w_ram is
10 subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
11 type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
13 signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000",
14 1 => "11100000000000001001000000000000",
15 2 => "11100000000010001001000000000000",
16 3 => "11100001000110010111011001101100",
17 others => x"00000000");
22 if rising_edge(clk) then
23 data_out <= ram(to_integer(UNSIGNED(rd_addr)));
26 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
30 end architecture behaviour;