From 7e9aca29a7c71af64c052e9271bace4e1f52bf24 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Sat, 11 Dec 2010 12:38:54 +0100 Subject: [PATCH] call/return --- cpu/sim/testcore.do | 4 ++++ cpu/src/r_w_ram_b.vhd | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do index 41ea364..c77feb0 100644 --- a/cpu/sim/testcore.do +++ b/cpu/sim/testcore.do @@ -68,4 +68,8 @@ add wave -radix hexadecimal /pipeline_tb/decode_st/reg_we add wave -radix hexadecimal /pipeline_tb/exec_st/gpmp_inst/psw +add wave -radix hexadecimal /pipeline_tb/addr_pin +add wave -radix hexadecimal /pipeline_tb/data_pin +add wave -radix hexadecimal /pipeline_tb/dmem_wr_en_pin + run 5000 ns diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index 0dbf3d4..14cc3be 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -12,7 +12,7 @@ architecture behaviour of r_w_ram is -- r0 = 0, r1 = 1, r2 = 3, r3 = A - signal ram : RAM_TYPE := ( 0 => "11101011000000000000000000010111", -- call +1 + signal ram : RAM_TYPE := ( 0 => "11101011000000000000000010000101", -- call +1 1 => "11101101000010000000000000111000", -- r1 = 7 2 => "11101101000100000000000000101000", -- r2 = 5 -- 2.25.1