3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
8 architecture behaviour of r_w_ram is
10 subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
11 type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
13 -- r0 = 0, r1 = 1, r2 = 3, r3 = A
15 signal ram : RAM_TYPE := ( 0 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1
16 1 => "11100000000110001000000000000000", --add r3, r1, r0 => r3 = 1
17 2 => "11100000001000011001000000000000", --add r4, r3, r2 => r4 = 2
18 3 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1
19 4 => "11100000000110001000000000000000", --add r3, r1, r0 => r3 = 1
20 5 => "11100000001000011001000000000000", --add r4, r3, r2 => r4 = 2
21 6 => "11101100000000001000000000000000", --cmp r0 , r1 => 0-1 => 0100
22 7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2
23 8 => "00000000001010101010000000000000", --addnq r5, r5, r4 => r5 = 4
24 9 => "11101100001000100000000000000000", --cmp r4 , r4 => 2-2 => 1001
25 10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix
26 11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB
27 12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1
28 13 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1
29 14 => "11100010000100001000000000000000", --and r2, r1, r0 => r2 = 0
30 15 => "11101100000000001000000000000000", --cmp r0 , r1 => 0-1 => 0100
31 16 => "10000000001010101010000000000001", --addabd r5, r5, r4 => r5 = 6
32 17 => "10110011101110001000010000110001", --orxltd r7, 1086 => r7 = 1086
33 18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2
34 19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4
35 others => x"F0000000");
41 if rising_edge(clk) then
42 data_out <= ram(to_integer(UNSIGNED(rd_addr)));
45 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
49 end architecture behaviour;