lustiger modelsim fix...

diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do
index fc2ff124c6ced39c40f543283521e879384df1ed..f2e2b79dabcb364f87f1a505f8b6ab04c00e8467 100644 (file)
--- a/cpu/sim/testcore1.do
+++ b/cpu/sim/testcore1.do
@@ -5,6 +5,8 @@ vcom -work work ../src/mem_pkg.vhd
 vcom -work work ../src/rom.vhd
 vcom -work work ../src/rom_b.vhd
 vcom -work work ../src/r_w_ram.vhd
+vcom -work work ../src/r_w_ram_be.vhd
+vcom -work work ../src/r_w_ram_be_b.vhd
 vcom -work work ../src/r_w_ram_b.vhd
 vcom -work work ../src/r2_w_ram.vhd
 vcom -work work ../src/r2_w_ram_b.vhd
@@ -140,6 +142,16 @@ add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w3_uart_
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w4_uart_receive
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/uart_data_read_nxt
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg.sel
-
-
-run 5000 ns
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_rx_inst/rx_data_nxt
+
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/reg_we
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/write_en
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_en
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_write_en
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_anysel
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.address
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
+add wave  -group test -radix hexadecimal /pipeline_tb/exec_st/dmem_write_en
+
+run 100000 ns

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index f9729920af1d30d3948afa49d48b699c300eaa9d..a7f14d9442c611e0b4820308107ec3409b31afba 100644 (file)
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -23,8 +23,8 @@ subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
 --constant BAUD_RATE : integer := 115200;
 --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
 -- constant CLK_PER_BAUD : integer := 434;
--- constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
-constant CLK_PER_BAUD : integer := 15; -- @modelsim
+constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+-- constant CLK_PER_BAUD : integer := 50; -- @modelsim
 
  component extension_uart is
         --some modules won't need all inputs/outputs

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index da886861d1cb98700e2b24352ef25f918ee7fca7..47406cab3f02f6b55dbf13bee70f23c3c9ab26a3 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -191,10 +191,11 @@ begin
        begin
                for i in 0 to 9 loop
                        rx_pin <= trans_data(i);
+                       report "bit: " & std_logic'image(trans_data(i));
                        dummy <= not dummy;
                        wait on dummy;
                        -- icwait(BAUD_COUNT);
-                       icwait(15);
+                       icwait(50);
                end loop;
        end txd;
 
@@ -204,6 +205,7 @@ begin
     -- initial reset
     -----------------------------------------------------------------------------
        sys_res_n_pin <= '0';
+       rx_pin <= '1';
 --     reg_w_addr_pin <= (others => '0');
 --     reg_wr_data_pin <= (others => '0');
 --     reg_we_pin <= '0';
@@ -215,9 +217,12 @@ begin
        
        icwait(10);
 
-       txd("0100000101");
+       txd("0000100101");
+       icwait(600);
+       icwait(600);
 
-       icwait(1000000000);
+       txd("0000100101");
+       icwait(600000000);
 
     ---------------------------------------------------------------------------
     -- exit testbench

diff --git a/cpu/src/rs232_rx_arc.vhd b/cpu/src/rs232_rx_arc.vhd
index 924a3ce9a6be8bc8aba7bed482f87ccfb622d05b..0a9df83efd043ea824540ad389a46121539673e5 100755 (executable)
--- a/cpu/src/rs232_rx_arc.vhd
+++ b/cpu/src/rs232_rx_arc.vhd
@@ -38,6 +38,7 @@ begin
                        state <= IDLE;
                        cnt <= 0;
                        rx_data_res_int <= x"00";
+                       rx_data_int <= (others => '0');
                        baud_cnt <= (others => '0');
                        sync <= (others => '1');