uart: bugfix fuer busy reset

diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do
index 885a80f38a8ab1f38299e29f8cf5fc92824427fa..fc2ff124c6ced39c40f543283521e879384df1ed 100644 (file)
--- a/cpu/sim/testcore1.do
+++ b/cpu/sim/testcore1.do
@@ -131,13 +131,15 @@ add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writebac
 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
 
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/reg_we
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/write_en
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_en
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_write_en
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_anysel
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
-add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.address
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bus_rx
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bus_tx
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co_nxt
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w2_uart_config
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w3_uart_send
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w4_uart_receive
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/uart_data_read_nxt
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg.sel
 
 
 run 5000 ns

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index 7df072ab5fa7d9be8ded77e94dfa4fd114bf38a5..09cec401b335ea2bcb8f1767de17d7faee7d5857 100644 (file)
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -17,8 +17,7 @@ signal        bd_rate : baud_rate_l;
 signal rx_data : std_logic_vector(7 downto 0);
 
 signal uart_int_nxt : std_logic;
-
-signal uart_data_read, uart_data_read_nxt : std_logic;
+signal uart_data_read_nxt : std_logic;
 
 begin
 
@@ -75,7 +74,6 @@ begin
                        w4_uart_receive <= (others=>'0');
                        tx_rdy_int <= '0';
                        new_tx_data <= '0';
-                       uart_data_read <= '0';
                        uart_int <= '0';
 
        elsif rising_edge(clk) then            
@@ -85,14 +83,14 @@ begin
                        w4_uart_receive <= w4_uart_receive_nxt;
                        new_tx_data <= new_tx_data_nxt;
                        tx_rdy_int <= tx_rdy;
-                       uart_data_read <= uart_data_read_nxt;
                        uart_int <= uart_int_nxt;
    end if;
 end process syn;
 
 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
 
-gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read)
+gwriten : process
+       (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read_nxt)
 
 variable tmp_data  : gp_register_t;
 
@@ -142,7 +140,7 @@ begin
                uart_int_nxt <= '1';
        end if;
        
-       if (uart_data_read = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
+       if (uart_data_read_nxt = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
                w1_st_co_nxt(1) <= '0';
        end if;
        

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index 9a2a52f3dd4a4aac5b3a8f12c0e4235014b876d9..f9729920af1d30d3948afa49d48b699c300eaa9d 100644 (file)
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -23,7 +23,8 @@ subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
 --constant BAUD_RATE : integer := 115200;
 --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
 -- constant CLK_PER_BAUD : integer := 434;
-constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+-- constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+constant CLK_PER_BAUD : integer := 15; -- @modelsim
 
  component extension_uart is
         --some modules won't need all inputs/outputs

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index e1135d411ac9ed4cfda5a391d7f9c6de13213815..da886861d1cb98700e2b24352ef25f918ee7fca7 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -193,7 +193,8 @@ begin
                        rx_pin <= trans_data(i);
                        dummy <= not dummy;
                        wait on dummy;
-                       icwait(BAUD_COUNT);
+                       -- icwait(BAUD_COUNT);
+                       icwait(15);
                end loop;
        end txd;
 

diff --git a/cpu/src/rom_b.vhd b/cpu/src/rom_b.vhd
index 36b344598d8bf9a99476f0a6dca2d6b0ddf2a62b..adc249d52801e3af10b83db2d98f510ee05657de 100644 (file)
--- a/cpu/src/rom_b.vhd
+++ b/cpu/src/rom_b.vhd
@@ -123,8 +123,8 @@ begin
 --                             when "00000000111" => data_out <= x"e7a00004";
 --                             when "00000001000" => data_out <= x"e7280004";
 --                     --      when "00000001001" => data_out <= x"eb7ffb81";
-       when "0000000" => data_out <= x"eb000183"; -- br+ main
-       when "0000001" => data_out <= x"eb000103"; -- br+ main
+       when "0000000" => data_out <= x"eb000181"; -- br main
+       when "0000001" => data_out <= x"eb000101"; -- br main
        when "0000010" => data_out <= x"eb000008"; -- ret
        when "0000011" => data_out <= x"ed510000"; -- ldi r10, UART_BASE@lo
        when "0000100" => data_out <= x"ed500002"; -- ldih r10, UART_BASE@hi