muh

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 722b196cfb640e5c09f9868c7ebf088318b804f1..b243fbabeaae7f3a54172386be36a40aa47b9c71 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -165,7 +165,13 @@ package core_pkg is
                        sseg3 : out std_logic_vector(0 to 6);
 
                        int_req : out interrupt_t;
-
+                       
+                       LCD_DATA_8 : out std_logic_vector(7 downto 0);
+                       LCD_BLON : out std_logic;
+                       LCD_RW : out std_logic;
+                       LCD_EN : out std_logic;
+                       LCD_RS : out std_logic;
+                       LCD_ON : out std_logic;
                        lcd_data : out std_logic_vector(6 downto 0)
                );
        end component writeback_stage;

diff --git a/cpu/src/core_top_c4de2_115.vhd b/cpu/src/core_top_c4de2_115.vhd
new file mode 100644 (file)
index 0000000..59426c8
--- /dev/null
+++ b/cpu/src/core_top_c4de2_115.vhd
@@ -0,0 +1,210 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+use work.extension_pkg.all;
+
+entity core_top_c4de2_115 is
+
+       port(
+               --System input pins
+               CLOCK_50        : in std_logic;
+               --Reset buttons
+               KEY : in std_logic_vector(0 to 3);
+
+               -- uart
+               UART_TXD : out std_logic;
+               UART_RXD : in std_logic;
+               -- bootrom led
+               LEDR : out std_logic_vector(0 to 17);
+               LEDG : out std_logic_vector(0 to 8);
+                       
+               HEX0 : out std_logic_vector(0 to 6);
+               HEX1 : out std_logic_vector(0 to 6);
+               HEX2 : out std_logic_vector(0 to 6);
+               HEX3 : out std_logic_vector(0 to 6);
+               
+               
+               LCD_DATA_8 : out std_logic_vector(7 downto 0);
+               LCD_BLON : out std_logic;
+               LCD_RW : out std_logic;
+               LCD_EN : out std_logic;
+               LCD_RS : out std_logic;
+               LCD_ON : out std_logic
+               
+               
+       );
+
+end core_top_c4de2_115;
+
+architecture behav of core_top_c4de2_115 is
+
+               constant SYNC_STAGES : integer := 2;
+               constant RESET_VALUE : std_logic := '0';
+
+               signal sys_clk, sys_res, soft_res : std_logic;
+               signal bus_tx, bus_rx : std_logic;
+               signal led2 : std_logic;
+               signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
+               
+               signal jump_result : instruction_addr_t;
+               signal jump_result_pin : instruction_addr_t;
+               signal prediction_result_pin : instruction_addr_t;
+               signal branch_prediction_bit_pin : std_logic;
+               signal alu_jump_bit_pin : std_logic;
+               signal instruction_pin : instruction_word_t;
+               signal prog_cnt_pin : instruction_addr_t;
+
+               signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+               signal reg_wr_data_pin : gp_register_t;
+               signal reg_we_pin : std_logic;
+               signal to_next_stage : dec_op;
+
+      signal result_pin : gp_register_t;--reg
+      signal result_addr_pin : gp_addr_t;--reg
+      signal addr_pin : word_t; --memaddr
+      signal data_pin : gp_register_t; --mem data --ureg
+      signal alu_jump_pin : std_logic;--reg
+      signal brpr_pin  : std_logic;  --reg
+      signal wr_en_pin : std_logic;--regop --reg
+      signal dmem_pin  : std_logic;--memop
+      signal dmem_wr_en_pin : std_logic;
+      signal hword_pin  : std_logic;
+      signal byte_s_pin : std_logic;
+                                
+                signal gpm_in_pin : extmod_rec;
+                signal gpm_out_pin : gp_register_t;
+                signal nop_pin : std_logic;
+                
+                signal sync : std_logic_vector(1 to SYNC_STAGES);
+                signal sync2 : std_logic_vector(1 to SYNC_STAGES);
+                signal sys_res_n, soft_res_n : std_logic;
+
+                signal int_req : interrupt_t;
+
+                signal new_im_data : std_logic;
+                signal im_addr, im_data : gp_register_t;
+--              signal led2 : std_logic;
+                
+                signal vers, vers_nxt : exec2wb_rec;
+begin
+       sys_clk <= CLOCK_50;
+       sys_res <= KEY(0);
+       soft_res <= KEY(1);
+       
+       UART_TXD <= bus_tx;
+       bus_rx <= UART_RXD;
+       
+       --bootrom status
+       LEDR(0) <= led2;
+       LEDR(1 to 17) <= (others => '0');
+       LEDG <= (others => '0');
+       
+       HEX0 <= sseg0;
+       HEX1 <= sseg1;
+       HEX2 <= sseg2;
+       HEX3 <= sseg3;
+
+       fetch_st : fetch_stage
+               generic map (
+       
+                       RESET_VALUE,
+                       '1'
+               )
+               
+               port map (
+               --System inputs
+                       clk => sys_clk, --: in std_logic;
+                       reset => sys_res_n, --: in std_logic;
+                       s_reset => soft_res_n,
+               
+               --Data inputs
+                       jump_result => jump_result_pin, --: in instruction_addr_t;
+                       prediction_result => prediction_result_pin, --: in instruction_addr_t;
+                       branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
+                       alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+                       int_req => int_req,
+               -- instruction memory program port :D
+                       new_im_data_in => new_im_data,
+                       im_addr => im_addr,
+                       im_data => im_data,
+               --Data outputs
+                       instruction => instruction_pin, --: out instruction_word_t
+                       prog_cnt => prog_cnt_pin,
+                       led2 => led2
+               );
+
+       decode_st : decode_stage
+               generic map (
+                       -- active reset value
+                       RESET_VALUE,
+                       -- active logic value
+                       '1'
+                       
+                       )
+               port map (
+               --System inputs
+                       clk => sys_clk, --: in std_logic;
+                       reset => sys_res_n and soft_res_n, -- : in std_logic;
+
+               --Data inputs
+                       instruction => instruction_pin, --: in instruction_word_t;
+                       prog_cnt => prog_cnt_pin,
+                       reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+                       reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
+                       reg_we => reg_we_pin, --: in std_logic;
+                       nop => nop_pin,
+
+               --Data outputs
+                       branch_prediction_res => prediction_result_pin, --: instruction_word_t;
+                       branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
+                       to_next_stage => to_next_stage
+               );
+
+          exec_st : execute_stage
+                generic map(RESET_VALUE)
+                port map(sys_clk, sys_res_n and soft_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
+
+                                                                        
+          writeback_st : writeback_stage
+                generic map(RESET_VALUE, '1', "altera", 434)
+                port map(sys_clk, sys_res_n and soft_res_n, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
+                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, 
+                                        new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req,    LCD_DATA_8, LCD_BLON, LCD_RW,
+                                        LCD_EN, LCD_RS, LCD_ON);
+
+
+
+syn: process(sys_clk, sys_res)
+
+begin
+
+       if sys_res = RESET_VALUE then
+       
+               sync <= (others => RESET_VALUE);
+       
+       elsif rising_edge(sys_clk) then
+                       sync(1) <= sys_res;
+                       for i in 2 to SYNC_STAGES loop
+                               sync(i) <= sync(i - 1);
+                       end loop;
+                       
+                       sync2(1) <= soft_res;
+                       for i in 2 to SYNC_STAGES loop
+                               sync2(i) <= sync2(i - 1);
+                       end loop;
+                               
+       end if;
+       
+end process;
+
+sys_res_n <= sync(SYNC_STAGES);
+soft_res_n <= sync2(SYNC_STAGES);
+nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
+jump_result <= prog_cnt_pin; --jump_result_pin;
+
+end behav;

diff --git a/cpu/src/extension_lcd_8.vhd b/cpu/src/extension_lcd_8.vhd
new file mode 100644 (file)
index 0000000..8c5d1c6
--- /dev/null
+++ b/cpu/src/extension_lcd_8.vhd
@@ -0,0 +1,25 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_pkg.all;
+use work.extension_imp_pkg.all;
+
+entity extension_lcd_8 is
+       generic ( RESET_VALUE : std_logic);
+       port(
+                       --System inputs
+                       clk :   in std_logic;
+                       reset : in std_logic;
+                       -- general extension interface
+                       ext_reg  : in extmod_rec;
+                       data_out : out gp_register_t;
+                       LCD_DATA : out std_logic_vector(7 downto 0);
+                       LCD_BLON : out std_logic;
+                       LCD_RW : out std_logic;
+                       LCD_EN : out std_logic;
+                       LCD_RS : out std_logic;
+                       LCD_ON : out std_logic
+               );
+end extension_lcd_8;

diff --git a/cpu/src/extension_lcd_b_8.vhd b/cpu/src/extension_lcd_b_8.vhd
new file mode 100644 (file)
index 0000000..db591a8
--- /dev/null
+++ b/cpu/src/extension_lcd_b_8.vhd
@@ -0,0 +1,273 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+
+
+use work.mem_pkg.all;
+use work.extension_pkg.all;
+use work.extension_lcd_pkg_8.all;
+
+architecture behav of extension_lcd_8 is
+
+constant CLK_Divide : integer := 16;
+
+signal w1_st_co, w1_st_co_nxt, w2_im_val, w2_im_val_nxt : gp_register_t;
+signal w3_im_notused, w3_im_notused_nxt, w4_im_notused, w4_im_notused_nxt : gp_register_t;
+
+signal lcd_count, lcd_count_nxt : integer := 0;
+signal lcd_st, lcd_st_nxt : std_logic_vector(1 downto 0);
+signal lcd_preStart, lcd_preStart_nxt, lcd_mStart, lcd_mStart_nxt, lcd_done, lcd_done_nxt : std_logic;
+signal lcd_en_int, lcd_en_nxt, lcd_start, lcd_start_nxt : std_logic;
+
+
+signal lcd_rom_addr, lcd_rom_addr_nxt : std_logic_vector(2 downto 0);
+signal lcd_rom_data : std_logic_vector(11 downto 0); -- eigentlich 8 downto 0, aber vhdl < 2008 kann 
+--keine laenge von bits bei hex angeben und binaer suckt
+
+type LCD_SETUP_STATE_TYPE is (SEND_DATA, WAIT_DONE, DO_WAIT, FETCH_NEW);
+signal lcd_set_st, lcd_set_st_nxt : LCD_SETUP_STATE_TYPE;
+signal lcd_set_delay, lcd_set_delay_nxt : std_logic_vector(17 downto 0);
+
+begin
+
+
+LCD_ON <= '1';
+LCD_BLON <= '1';
+LCD_RW <= '0';
+
+LCD_EN <= lcd_en_int;
+
+LCD_DATA <= lcd_rom_data(7 downto 0);
+LCD_RS <= lcd_rom_data(8);
+
+syn : process (clk, reset)
+begin
+   if (reset = RESET_VALUE) then
+               w1_st_co <= (others => '0');
+               w2_im_val <= (others => '0');
+               w3_im_notused <= (others => '0');
+               w4_im_notused <= (others => '0');
+               
+               --lcd ctrl
+               lcd_en_int <= '0';
+               lcd_st <= "00";
+               lcd_done <= '0';
+               lcd_preStart <= '0';
+               lcd_start <= '0';
+               lcd_mStart <= '0';
+               lcd_count <= 0;
+               
+               --lcd_setup
+               lcd_rom_addr <= (others => '0');
+               lcd_set_st <= SEND_DATA;
+               lcd_set_delay <= (others => '0');
+               
+       elsif rising_edge(clk) then
+               w1_st_co <= w1_st_co_nxt;
+               w2_im_val <= w2_im_val_nxt;
+               w3_im_notused <= w3_im_notused_nxt;
+               w4_im_notused <= w4_im_notused_nxt;
+               
+               --lcd ctrl
+               lcd_en_int <= lcd_en_nxt;
+               lcd_st <= lcd_st_nxt;
+               lcd_done <= lcd_done_nxt;
+               lcd_preStart <= lcd_preStart_nxt;
+               lcd_start <= lcd_start_nxt;
+               lcd_mStart <= lcd_mStart_nxt;
+               lcd_count <= lcd_count_nxt;
+
+               --lcd setup
+               lcd_rom_addr <= lcd_rom_addr_nxt;
+               lcd_set_st <= lcd_set_st_nxt;
+               lcd_set_delay <= lcd_set_delay_nxt;
+               
+       
+   end if;
+end process syn;
+
+-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
+
+gwriten : process (ext_reg, w1_st_co, w2_im_val, w3_im_notused, w4_im_notused)
+variable tmp_data : gp_register_t;
+begin
+       w1_st_co_nxt <= w1_st_co;
+       w2_im_val_nxt <= w2_im_val;
+       w3_im_notused_nxt <= w3_im_notused;
+       w4_im_notused_nxt <= w4_im_notused;
+
+       -- timer logic
+       if (w1_st_co(0) = '1') then -- timer enabled?
+               w2_im_val_nxt <= std_logic_vector(IEEE.numeric_std.unsigned(w2_im_val) + 1);
+               -- n00b overflow (logic elements sparen...)
+               if(w2_im_val(31) = '1') then 
+                       w1_st_co_nxt(16) <= '1';
+               end if;
+       end if;
+
+       if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
+               tmp_data := (others =>'0');                     
+               for i in 0 to 3 loop
+                       if ext_reg.byte_en(i) = '1' then
+                               tmp_data(((i+1)*byte_t'length-1) downto i*byte_t'length) := ext_reg.data(((i+1)*byte_t'length-1) downto i*byte_t'length);
+                       end if;
+               end loop;
+
+               case ext_reg.addr(1 downto 0) is
+               when "00" => -- status/config
+                       w1_st_co_nxt <= tmp_data;
+               when "01" => -- timer value
+                       w2_im_val_nxt <= tmp_data;
+               when "10" => null;
+               when "11" => null;
+               when others => null;
+               end case;
+       end if;
+end process gwriten;
+
+gread : process (clk, ext_reg, w1_st_co, w2_im_val, w3_im_notused, w4_im_notused)
+variable tmp_data : gp_register_t;
+begin
+       tmp_data := (others => '0');
+       if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
+               case ext_reg.addr(1 downto 0) is
+               when "00" => put_word_be(tmp_data, w1_st_co, ext_reg.byte_en);
+               when "01" => put_word_be(tmp_data, w2_im_val, ext_reg.byte_en);
+               when "10" => put_word_be(tmp_data, w3_im_notused, ext_reg.byte_en);
+               when "11" => put_word_be(tmp_data, w4_im_notused, ext_reg.byte_en);
+               when others => null;
+               end case;
+       end if;
+       data_out <= tmp_data;
+end process gread;
+
+
+
+lcd_setup : process(clk, lcd_set_st, lcd_start, lcd_set_delay, lcd_rom_addr, lcd_done)
+begin
+       lcd_set_st_nxt <= lcd_set_st;
+       lcd_start_nxt <= lcd_start;
+       lcd_set_delay_nxt <= lcd_set_delay;
+       lcd_rom_addr_nxt <= lcd_rom_addr;
+       
+       if lcd_rom_addr < "101000" then
+               case lcd_set_st is
+                       when SEND_DATA =>
+                               lcd_start_nxt <= '1';
+                               lcd_set_st_nxt <= WAIT_DONE;
+
+                       when WAIT_DONE =>
+                               if lcd_done = '1' then
+                                       lcd_set_st_nxt <= DO_WAIT;
+                                       lcd_start_nxt <= '0';
+                               end if;
+
+                       when DO_WAIT =>
+                               if lcd_set_delay < x"3fffe" then
+                                       lcd_set_delay_nxt <= lcd_set_delay + 1;
+                               else
+                                       lcd_set_delay_nxt <= (others => '0');
+                                       lcd_set_st_nxt <= FETCH_NEW;
+                               end if;
+
+                       when FETCH_NEW =>
+                               lcd_rom_addr_nxt <= lcd_rom_addr + 1;
+                               lcd_set_st_nxt <= SEND_DATA;
+               end case;
+       end if;
+               
+end process lcd_setup;
+
+lcd_ctrl : process(clk, lcd_en_int, lcd_count, lcd_mStart, lcd_start, lcd_done, lcd_preStart, lcd_st)
+begin
+       lcd_en_nxt <= lcd_en_int;
+       lcd_count_nxt <= lcd_count;
+       lcd_mStart_nxt <= lcd_mStart;
+       
+       lcd_preStart_nxt <= lcd_start;
+       lcd_done_nxt <= lcd_done;
+       
+       --start detection
+       if lcd_preStart = '0' and lcd_start = '1' then
+               lcd_mStart_nxt <= '1';
+               lcd_done_nxt <= '0';
+       end if;
+       lcd_st_nxt <= lcd_st;
+       case lcd_st is
+               when "00" =>
+                       if  lcd_mStart = '1' then
+                               lcd_st_nxt <= "01"; -- wait setup
+                       else
+                               lcd_st_nxt <= "00";
+                       end if;
+               when "01" =>
+                       lcd_en_nxt <= '1';
+                       lcd_st_nxt <= "10";
+               when "10" =>
+                       if(lcd_count < CLK_Divide) then
+                               lcd_count_nxt <= lcd_count+1;
+                       else
+                               lcd_st_nxt <= "11";
+                       end if;
+               when "11" =>
+                       lcd_en_nxt <= '0';
+                       lcd_mStart_nxt <= '0';
+                       lcd_done_nxt  <= '1';
+                       lcd_count_nxt <= 0;
+                       lcd_st_nxt <= "00";
+       end case;
+
+
+end process lcd_ctrl;
+
+lcd_data_rom : process(lcd_rom_addr)
+begin
+       case lcd_rom_addr is
+               --init of display
+               when "000" => lcd_rom_data <= x"038";
+               when "001" => lcd_rom_data <= x"00c";
+               when "010" => lcd_rom_data <= x"038";
+               when "011" => lcd_rom_data <= x"00c";
+               when "100" => lcd_rom_data <= x"001";
+               when "101" => lcd_rom_data <= x"006";
+               when "110" => lcd_rom_data <= x"080";
+               when others => lcd_rom_data <= x"0b0"; --goto 0,0
+               --      Line 1
+               --when "000111" => lcd_rom_data <= x"120";      --      Welcome to the
+               --when "001000" => lcd_rom_data <= x"13C";
+               --when "001001" => lcd_rom_data <= x"133";
+               
+               --when "010110" => lcd_rom_data <= x"120";
+               --      Change Line
+               --when "010111" => lcd_rom_data <= x"0c0";
+               --      Line 2
+               --when "011000" => lcd_rom_data <= x"120";      --      Altera DE2-70
+               --when "011001" => lcd_rom_data <= x"141";      
+               --when "011010" => lcd_rom_data <= x"085"; --back to upper line + forward
+               --when "011011" => lcd_rom_data <= x"174";
+--             when "011100" => lcd_rom_data <= x"165";
+--             when "011101" => lcd_rom_data <= x"172";
+--             when "011110" => lcd_rom_data <= x"161";
+--             when "011111" => lcd_rom_data <= x"120";
+--             when "100000" => lcd_rom_data <= x"144";
+--             when "100010" => lcd_rom_data <= x"145";
+--             when "100011" => lcd_rom_data <= x"132";
+--             when "100100" => lcd_rom_data <= x"1b0";
+--             when "100101" => lcd_rom_data <= x"131";
+--             when "100110" => lcd_rom_data <= x"131";
+--             when "100111" => lcd_rom_data <= x"135";
+--             when "101000" => lcd_rom_data <= x"120";
+--             when others => lcd_rom_data <= x"120";
+       end case;
+end process lcd_data_rom;
+
+
+-------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
+-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
+-------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
+end behav;

diff --git a/cpu/src/extension_lcd_pkg_8.vhd b/cpu/src/extension_lcd_pkg_8.vhd
new file mode 100644 (file)
index 0000000..b1d2fb0
--- /dev/null
+++ b/cpu/src/extension_lcd_pkg_8.vhd
@@ -0,0 +1,27 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_pkg.all;
+
+package extension_lcd_pkg_8 is
+       component extension_lcd_8 is
+       generic ( RESET_VALUE : std_logic);
+       port(
+                       --System inputs
+                       clk :   in std_logic;
+                       reset : in std_logic;
+                       -- general extension interface
+                       ext_reg  : in extmod_rec;
+                       data_out : out gp_register_t;
+                       LCD_DATA : out std_logic_vector(7 downto 0);
+                       LCD_BLON : out std_logic;
+                       LCD_RW : out std_logic;
+                       LCD_EN : out std_logic;
+                       LCD_RS : out std_logic;
+                       LCD_ON : out std_logic
+               );
+       end component extension_lcd_8;
+end package extension_lcd_pkg_8;

diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd
index 31cc54251f7c90b9d4cee4d53a2df990acc2babf..5220f7d90f0db05861a9f8045d083afbad7a95cf 100644 (file)
--- a/cpu/src/extension_pkg.vhd
+++ b/cpu/src/extension_pkg.vhd
@@ -43,6 +43,7 @@ constant EXT_INT_ADDR:          ext_addrid_t := x"0000202";
 constant EXT_IMP_ADDR:   ext_addrid_t := x"0000203";
 constant EXT_TIMER_ADDR:  ext_addrid_t := x"0000204";
 constant EXT_LCD_ADDR:    ext_addrid_t := x"0000205";
+constant EXT_LCD_8_ADDR:  ext_addrid_t := x"0000206";
 -- dummy addressen
 constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB";
 constant EXT_AC97_ADDR:   ext_addrid_t := x"FFFFFFD";

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 4f2c231ffcf25c6f5fb7c4ca0411d7b49cc22637..460f34328f9aef2406506e4ddee85b7e25266162 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -50,6 +50,13 @@ entity writeback_stage is
                        sseg3 : out std_logic_vector(0 to 6);
 
                        int_req : out interrupt_t;
+                       
+                       LCD_DATA_8 : out std_logic_vector(7 downto 0);
+                       LCD_BLON : out std_logic;
+                       LCD_RW : out std_logic;
+                       LCD_EN : out std_logic;
+                       LCD_RS : out std_logic;
+                       LCD_ON : out std_logic;
 
                        lcd_data : out std_logic_vector(6 downto 0)
                );

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 8b208b9d123a7b4bd7aef03b2ac093aaf6a8aa38..641be540774e293ed22f8d1b01d5fddb4fe84e4d 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -12,6 +12,7 @@ use work.extension_7seg_pkg.all;
 use work.extension_imp_pkg.all;
 use work.extension_timer_pkg.all;
 use work.extension_lcd_pkg.all;
+use work.extension_lcd_pkg_8.all;
 
 architecture behav of writeback_stage is
 
@@ -20,8 +21,8 @@ signal data_addr : word_t;
 
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
-signal ext_uart,ext_timer,ext_gpmp,ext_7seg,ext_int,ext_imp, ext_lcd :  extmod_rec;
-signal ext_uart_out, ext_timer_out, ext_gpmp_out, ext_int_out,ext_imp_out, ext_lcd_out : gp_register_t;
+signal ext_uart,ext_timer,ext_gpmp,ext_7seg,ext_int,ext_imp, ext_lcd, ext_lcd_8 :  extmod_rec;
+signal ext_uart_out, ext_timer_out, ext_gpmp_out, ext_int_out,ext_imp_out, ext_lcd_out, ext_lcd_out_8 : gp_register_t;
 
 --signal int_req : interrupt_t;
 signal uart_int : std_logic;
@@ -136,6 +137,11 @@ lcd : extension_lcd
        generic map(RESET_VALUE)
        port map(clk, reset, ext_lcd, ext_lcd_out, lcd_data);
        
+lcd8 : extension_lcd_8
+       generic map(RESET_VALUE)
+       port map(clk, reset, ext_lcd_8, ext_lcd_out_8, LCD_DATA_8, LCD_BLON,
+               LCD_RW, LCD_EN, LCD_RS, LCD_ON);
+       
 syn: process(clk, reset)
 
 begin
@@ -327,7 +333,7 @@ begin
 end process;
 
 
-addr_de_mult: process(wb_reg, wb_reg_nxt, ram_data, sel_nxt, ext_uart_out, ext_gpmp_out, ext_timer_out)
+addr_de_mult: process(wb_reg, wb_reg_nxt, ram_data, sel_nxt, ext_uart_out, ext_gpmp_out, ext_timer_out, ext_lcd_out)
 variable wr_en, enable  : std_logic; -- these are all registered
 variable byte_en : byte_en_t; -- if a module needs the nxt signals it has to manually select them
 variable addr : ext_addr_t;   -- for example the data memory, because it already has input registers
@@ -350,6 +356,7 @@ begin
   ext_gpmp.sel <='0';
   ext_int.sel <= '0';
   ext_imp.sel <= '0';
+  ext_lcd.sel <= '0';
   
   ext_uart.wr_en <= wr_en;
   ext_7seg.wr_en <= wr_en;
@@ -357,7 +364,8 @@ begin
   ext_lcd.wr_en <= wr_en;
   ext_gpmp.wr_en <= wr_en;
   ext_int.wr_en <= wr_en;  
-  ext_imp.wr_en <= wr_en;  
+  ext_imp.wr_en <= wr_en;
+  ext_lcd.wr_en <= wr_en;
 
   ext_uart.byte_en <= byte_en;
   ext_7seg.byte_en <= byte_en;
@@ -365,7 +373,8 @@ begin
   ext_lcd.byte_en <= byte_en;
   ext_gpmp.byte_en <= byte_en;
   ext_int.byte_en <= byte_en;  
-  ext_imp.byte_en <= byte_en; 
+  ext_imp.byte_en <= byte_en;
+  ext_lcd.byte_en <= byte_en;
 
   ext_uart.addr <= addr;
   ext_7seg.addr <= addr;
@@ -374,6 +383,7 @@ begin
   ext_gpmp.addr <= addr;
   ext_int.addr <= addr;
   ext_imp.addr <= addr;
+  ext_lcd.addr <= addr;
 
   ext_uart.data <= data;
   ext_7seg.data <= data;
@@ -382,6 +392,7 @@ begin
   ext_gpmp.data <= data;
   ext_int.data <= data;
   ext_imp.data <= data;
+  ext_lcd.data <= data;
 
    -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
  case addrid is
@@ -480,6 +491,11 @@ begin
                                -- when others => null;
                        -- end case;
        -- hier kann man weiter extensions adden :) Konstanten sind im extension pkg definiert 
+       
+       when EXT_LCD_8_ADDR =>
+               ext_lcd.sel <= enable;
+               ext_anysel <= enable;
+       
        when others => ext_anysel <= '0';
        end case;
        

diff --git a/progs/Makefile b/progs/Makefile
index 86817a3d84ee07472935daf56063bfcffa0007e0..a1d1ce58a16c6397fb65de52c83a20cc82ab0642 100644 (file)
--- a/progs/Makefile
+++ b/progs/Makefile
@@ -3,6 +3,7 @@ SHELL := bash
 HN := $(shell hostname)
 TILABHOSTS := $(shell echo ti{1..41}) apps1
 STEFANHOST := ubuntu
+MPHOST := mp-lap
 
 ifeq ($(findstring $(HN), $(TILABHOSTS)), $(HN))
 DPROGFLAGS := -d /dev/ttyS0 -b 9600
@@ -10,10 +11,13 @@ else
 ifeq ($(findstring $(HN), $(STEFANHOST)), $(HN))
 DPROGFLAGS := -d /dev/ttyS0 -b 115200
 else
+ifeq ($(findstring $(HN), $(MPHOST)), $(HN))
+DPROGFLAGS := -d /dev/ttyS0 -b 115200
+else
 DPROGFLAGS := -d /dev/ttyUSB0 -b 115200
 endif
 endif
-
+endif
 
 all: fibmmem.prog