cpu/src/core_top_s3e.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7 use work.extension_pkg.all;
   8
   9 entity core_top is
  10
  11         port(
  12                 --System input pins
  13                    sys_res : in std_logic;
  14                         sys_clk : in std_logic;
  15 --                      result : out gp_register_t;
  16 --                      reg_wr_data : out gp_register_t
  17                   -- uart
  18                         bus_tx : out std_logic;
  19                         bus_rx : in std_logic;
  20
  21                         sseg0 : out std_logic_vector(0 to 6);
  22                         sseg1 : out std_logic_vector(0 to 6);
  23                         sseg2 : out std_logic_vector(0 to 6);
  24                         sseg3 : out std_logic_vector(0 to 6)
  25                 );
  26
  27 end core_top;
  28
  29 architecture behav of core_top is
  30
  31                 constant SYNC_STAGES : integer := 2;
  32                 constant RESET_VALUE : std_logic := '0';
  33
  34                 signal jump_result : instruction_addr_t;
  35                 signal jump_result_pin : instruction_addr_t;
  36                 signal prediction_result_pin : instruction_addr_t;
  37                 signal branch_prediction_bit_pin : std_logic;
  38                 signal alu_jump_bit_pin : std_logic;
  39                 signal instruction_pin : instruction_word_t;
  40                 signal prog_cnt_pin : instruction_addr_t;
  41
  42                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  43                 signal reg_wr_data_pin : gp_register_t;
  44                 signal reg_we_pin : std_logic;
  45                 signal to_next_stage : dec_op;
  46
  47 --              signal reg1_rd_data_pin : gp_register_t;
  48 --              signal reg2_rd_data_pin : gp_register_t;
  49
  50                  signal result_pin : gp_register_t;--reg
  51                  signal result_addr_pin : gp_addr_t;--reg
  52                  signal addr_pin : word_t; --memaddr
  53                  signal data_pin : gp_register_t; --mem data --ureg
  54                  signal alu_jump_pin : std_logic;--reg
  55                  signal brpr_pin  : std_logic;  --reg
  56                  signal wr_en_pin : std_logic;--regop --reg
  57                  signal dmem_pin  : std_logic;--memop
  58                  signal dmem_wr_en_pin : std_logic;
  59                  signal hword_pin  : std_logic;
  60                  signal byte_s_pin : std_logic;
  61
  62                  signal gpm_in_pin : extmod_rec;
  63                  signal gpm_out_pin : gp_register_t;
  64                  signal nop_pin : std_logic;
  65
  66                  signal sync : std_logic_vector(1 to SYNC_STAGES);
  67                  signal sys_res_n : std_logic;
  68
  69                  signal int_req : interrupt_t;
  70
  71                  signal vers, vers_nxt : exec2wb_rec;
  72 begin
  73
  74         fetch_st : fetch_stage
  75                 generic map (
  76
  77                         '0',
  78                         '1'
  79                 )
  80
  81                 port map (
  82                 --System inputs
  83                         clk => sys_clk, --: in std_logic;
  84                         reset => sys_res_n, --: in std_logic;
  85
  86                 --Data inputs
  87                         jump_result => jump_result_pin, --: in instruction_addr_t;
  88                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  89                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  90                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  91                         int_req => int_req,
  92
  93                 --Data outputs
  94                         instruction => instruction_pin, --: out instruction_word_t
  95                         prog_cnt => prog_cnt_pin
  96                 );
  97
  98         decode_st : decode_stage
  99                 generic map (
 100                         -- active reset value
 101                         '0',
 102                         -- active logic value
 103                         '1'
 104
 105                         )
 106                 port map (
 107                 --System inputs
 108                         clk => sys_clk, --: in std_logic;
 109                         reset => sys_res_n, -- : in std_logic;
 110
 111                 --Data inputs
 112                         instruction => instruction_pin, --: in instruction_word_t;
 113                         prog_cnt => prog_cnt_pin,
 114                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 115                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
 116                         reg_we => reg_we_pin, --: in std_logic;
 117                         nop => nop_pin,
 118
 119                 --Data outputs
 120                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 121                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 122                         to_next_stage => to_next_stage
 123                 );
 124
 125           exec_st : execute_stage
 126                 generic map('0')
 127                 port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
 128                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 129
 130
 131                         vers_nxt.result <= result_pin;
 132                         vers_nxt.result_addr <= result_addr_pin;
 133                         vers_nxt.address <= addr_pin;
 134                         vers_nxt.ram_data <= data_pin;
 135                         vers_nxt.alu_jmp <= alu_jump_pin;
 136                         vers_nxt.br_pred <= brpr_pin;
 137                         vers_nxt.write_en <= wr_en_pin;
 138                         vers_nxt.dmem_en <= dmem_pin;
 139                         vers_nxt.dmem_write_en <= dmem_wr_en_pin;
 140                         vers_nxt.hword <= hword_pin;
 141                         vers_nxt.byte_s <= byte_s_pin;
 142
 143 --          writeback_st : writeback_stage
 144 --                generic map('0', '1')
 145 --                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 146 --                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 147 --                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
 148 --
 149
 150                         writeback_st : writeback_stage
 151                 generic map('0', '1', "s3e")
 152                 port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
 153                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
 154                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin,
 155                                 alu_jump_bit_pin,bus_tx, bus_rx, open, open, open, sseg0, sseg1, sseg2, sseg3, int_req);
 156
 157
 158 syn: process(sys_clk, sys_res)
 159
 160 begin
 161
 162         if sys_res = '0' then
 163 --                      vers.result <= (others => '0');
 164 --                      vers.result_addr <= (others => '0');
 165 --                      vers.address <= (others => '0');
 166 --                      vers.ram_data <= (others => '0');
 167 --                      vers.alu_jmp <= '0';
 168 --                      vers.br_pred <= '0';
 169 --                      vers.write_en <= '0';
 170 --                      vers.dmem_en <= '0';
 171 --                      vers.dmem_write_en <= '0';
 172 --                      vers.hword <= '0';
 173 --                      vers.byte_s <= '0';
 174
 175                 sync <= (others => '0');
 176
 177         elsif rising_edge(sys_clk) then
 178 --              vers <= vers_nxt;
 179                         sync(1) <= sys_res;
 180                         for i in 2 to SYNC_STAGES loop
 181                                 sync(i) <= sync(i - 1);
 182                         end loop;
 183
 184         end if;
 185
 186 end process;
 187
 188 sys_res_n <= sync(SYNC_STAGES);
 189
 190 --init : process(all)
 191
 192 --begin
 193 --      jump_result_pin <= (others => '0');
 194 --      alu_jump_bit_pin <= '0';
 195 --      reg_w_addr_pin <= (others => '0');
 196 --      reg_wr_data_pin <= (others => '0');
 197 --      reg_we_pin <= '0';
 198
 199 --end process;
 200
 201 --      result <= result_pin;
 202         nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
 203
 204         jump_result <= prog_cnt_pin; --jump_result_pin;
 205 --      sys_res <= '1';
 206
 207 --      reg_wr_data <= reg_wr_data_pin;
 208
 209 end behav;