From: Markus Hofstätter Date: Mon, 29 Nov 2010 13:58:15 +0000 (+0100) Subject: ldi add finished X-Git-Tag: bootrom_v1~116 X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=commitdiff_plain;h=187d20b4c2e9b6aa3a79d9cd19aa0204de9733db ldi add finished --- diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd index 1bb83de..634c7d1 100755 --- a/cpu/src/alu_b.vhd +++ b/cpu/src/alu_b.vhd @@ -102,7 +102,7 @@ begin result_v := shift_result; when LDST_OP => if op_detail(IMM_OPT) = '1' then - result_v := right_operand; + result_v.result := right_operand; end if; end case; diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd index ab0ee7e..d1b49c1 100644 --- a/cpu/src/decoder_b.vhd +++ b/cpu/src/decoder_b.vhd @@ -225,8 +225,8 @@ begin if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then instr_s.immediate(31 downto 16) := (others => '1'); end if; - instr_s.immediate(14 downto 0) := instruction(14 downto 0); - instr_s.immediate(WORD_WIDTH-1 downto 15) := (others => '0'); + instr_s.immediate(11 downto 0) := instruction(14 downto 3); + instr_s.immediate(WORD_WIDTH-1 downto 12) := (others => '0'); instr_s.op_detail(IMM_OPT) := '1'; end if; end if; diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index 4f1a0e0..6db0659 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -12,9 +12,9 @@ architecture behaviour of r_w_ram is -- r0 = 0, r1 = 1, r2 = 3, r3 = A - signal ram : RAM_TYPE := ( 0 => "11100001000010001000000000111000", -- r1 = 7 - 1 => "11100001000100010000000000101000", -- r2 = 5 - 2 => "11100001000110011000000000100000", -- r3 = 4 + signal ram : RAM_TYPE := ( 0 => "11101101000010000000000000111000", -- r1 = 7 + 1 => "11101101000100000000000000101000", -- r2 = 5 + 2 => "11101101000110000000000000100000", -- r3 = 4 3 => "11100000001000010001100000000000", -- r4 = r2 + r3 4 => "11100010001010100000100000000000", -- r5 = r4 and r1 others => x"F0000000");