case op_group is
when ADDSUB_OP =>
result_v := add_result;
- addr(DATA_ADDR_WIDTH + 2) <= '0';
+ addr(DATA_ADDR_WIDTH + 3) <= '0';
when AND_OP =>
result_v := and_result;
- addr(DATA_ADDR_WIDTH + 2) <= '0';
+ addr(DATA_ADDR_WIDTH + 3) <= '0';
when OR_OP =>
result_v := or_result;
- addr(DATA_ADDR_WIDTH + 2) <= '0';
+ addr(DATA_ADDR_WIDTH + 3) <= '0';
when XOR_OP =>
result_v := xor_result;
- addr(DATA_ADDR_WIDTH + 2) <= '0';
+ addr(DATA_ADDR_WIDTH + 3) <= '0';
when SHIFT_OP =>
result_v := shift_result;
- addr(DATA_ADDR_WIDTH + 2) <= '0';
+ addr(DATA_ADDR_WIDTH + 3) <= '0';
when LDST_OP =>
res_prod := '0';
mem_op := '1';
res_prod := '1';
mem_op := '0';
- addr(DATA_ADDR_WIDTH + 2) <= '0';
+ addr(DATA_ADDR_WIDTH + 3) <= '0';
end if;
if op_detail(ST_OPT) = '1' then
mem_en := '1';
constant REG_ZERO : gp_register_t := (others => '0');
constant INSTR_ADDR_WIDTH : INTEGER := 32;
- constant PHYS_INSTR_ADDR_WIDTH : INTEGER := 11;
+ constant PHYS_INSTR_ADDR_WIDTH : INTEGER := 10;
constant ROM_INSTR_ADDR_WIDTH : INTEGER := 7;
constant REG_ADDR_WIDTH : INTEGER := 4;
- constant DATA_ADDR_WIDTH : INTEGER := 11;
+ constant DATA_ADDR_WIDTH : INTEGER := 10;
constant PHYS_DATA_ADDR_WIDTH : INTEGER := 32;
constant NUM_OP_OPT_WIDTH : INTEGER := 6;
constant UART_INT_EN_BIT : integer := 1;
constant GLOBAL_INT_EN_BIT : integer := 0;
- constant UART_INT_VECTOR : std_logic_vector(PHYS_INSTR_ADDR_WIDTH-1 downto 0) := "00000000001"; --integer := 1;
+ constant UART_INT_VECTOR : std_logic_vector(PHYS_INSTR_ADDR_WIDTH-1 downto 0) := (0 => '1', others => '0');
type instruction_rec is record
--Data outputs
-- reg1_rd_data : out gp_register_t;
-- reg2_rd_data : out gp_register_t;
- branch_prediction_res : out instruction_word_t;
+ branch_prediction_res : out instruction_addr_t;
branch_prediction_bit : out std_logic;
to_next_stage : out dec_op
--Data outputs
-- reg1_rd_data : out gp_register_t;
-- reg2_rd_data : out gp_register_t;
- branch_prediction_res : out instruction_word_t;
+ branch_prediction_res : out instruction_addr_t;
branch_prediction_bit : out std_logic;
to_next_stage : out dec_op
if (instr_pc = x"0000007f" and rom_ram = ROM_USE) then
rom_ram_nxt <= RAM_USE;
- -- TODO: wenn genau auf adresse 0 im RAM ein br steht kracht es... :/
- instr_r_addr_nxt <= x"00000000";
+ instr_r_addr_nxt <= (others => '0');
end if;
if (reset = RESET_VALUE) then
out_logic : process (instr_r_addr, alu_jump_bit, int_req, jump_result)
begin
- prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
- prog_cnt(31 downto 11) <= (others => '0');
+ prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
+ prog_cnt(INSTR_ADDR_WIDTH-1 downto PHYS_INSTR_ADDR_WIDTH) <= (others => '0');
if (int_req /= IDLE and alu_jump_bit = LOGIC_ACT ) then
- prog_cnt(10 downto 0) <= jump_result(10 downto 0);
+ prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= jump_result(PHYS_INSTR_ADDR_WIDTH-1 downto 0);
end if;
end process;
if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
jump_addr <= data_ram_read;
else
- jump_addr <= result;
+ jump_addr <= result;
end if;
-- if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
data_addr <= (others => '0');
dmem_we <= '0';
- if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
+ if (wb_reg.address(DATA_ADDR_WIDTH+3) /= '1') then
data_out := data_ram_read;
else
reg_we_v := reg_we_v and ext_anysel;
data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length);
- if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
+ if (wb_reg_nxt.address(DATA_ADDR_WIDTH+3) /= '1') then
data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
dmem_we <= wb_reg_nxt.dmem_write_en;
end if;