2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
6 use work.common_pkg.all;
9 architecture behav of fetch_stage is
11 signal instr_w_addr : instruction_addr_t;
12 signal instr_r_addr : instruction_addr_t;
13 signal instr_r_addr_nxt : instruction_addr_t;
14 signal instr_we : std_logic;
15 signal instr_wr_data : instruction_word_t;
16 signal instr_rd_data_rom, instr_rd_data : instruction_word_t;
17 signal rom_ram, rom_ram_nxt : std_logic;
21 instruction_ram : r_w_ram --rom
23 PHYS_INSTR_ADDR_WIDTH,
29 im_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
30 instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
44 instr_r_addr_nxt(ROM_INSTR_ADDR_WIDTH-1 downto 0),
49 syn: process(clk, reset)
53 if (reset = RESET_VALUE) then
54 instr_r_addr <= (others => '0');
57 elsif rising_edge(clk) then
58 instr_r_addr <= instr_r_addr_nxt;
59 rom_ram <= rom_ram_nxt;
60 led2 <= rom_ram; --rom_ram_nxt;
66 asyn: process(reset, s_reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
67 variable instr_pc : instruction_addr_t;
69 rom_ram_nxt <= rom_ram;
73 instruction <= instr_rd_data_rom;
75 instruction <= instr_rd_data;
77 instruction <= x"F0000000";
79 instr_pc := std_logic_vector(unsigned(instr_r_addr) + 1);
80 instr_r_addr_nxt <= instr_pc;
82 if (instr_pc = x"0000007f" and rom_ram = ROM_USE) then
83 rom_ram_nxt <= RAM_USE;
84 instr_r_addr_nxt <= (others => '0');
87 if (reset = RESET_VALUE) then
88 instr_r_addr_nxt <= (others => '0');
91 if (alu_jump_bit = LOGIC_ACT and int_req = IDLE) then
92 instr_r_addr_nxt <= jump_result;
93 instruction(31 downto 28) <= "1111";
94 elsif (branch_prediction_bit = LOGIC_ACT) then
95 instr_r_addr_nxt <= prediction_result;
100 instruction(31 downto 0) <= (others => '0');
101 instruction(31 downto 28) <= "1110";
102 instruction(27 downto 23) <= "10110";
103 instruction(PHYS_INSTR_ADDR_WIDTH + 7 - 1 downto 7) <= UART_INT_VECTOR;
104 instruction(6 downto 4) <= "001";
105 instruction(3 downto 2) <= "01";
106 instruction(1 downto 0) <= "10";
108 -- instr_r_addr_nxt <= instr_r_addr;
112 if (s_reset = RESET_VALUE) then
113 rom_ram_nxt <= RAM_USE;
114 instr_r_addr_nxt <= (others => '0');
119 out_logic : process (instr_r_addr, alu_jump_bit, int_req, jump_result)
122 prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
123 prog_cnt(INSTR_ADDR_WIDTH-1 downto PHYS_INSTR_ADDR_WIDTH) <= (others => '0');
125 if (int_req /= IDLE and alu_jump_bit = LOGIC_ACT ) then
126 prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= jump_result(PHYS_INSTR_ADDR_WIDTH-1 downto 0);