ram: reducing instr- and dataram

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index bd78302391114d40298521a502406204c8dbd839..746fbc3489e85f38a74e287224d97e8e7f481b9d 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -122,19 +122,19 @@ begin
        case op_group is
        when ADDSUB_OP =>
                result_v := add_result;
        case op_group is
        when ADDSUB_OP =>
                result_v := add_result;

-               addr(DATA_ADDR_WIDTH + 2) <= '0';
+               addr(DATA_ADDR_WIDTH + 3) <= '0';

        when AND_OP =>
                result_v := and_result;
        when AND_OP =>
                result_v := and_result;

-               addr(DATA_ADDR_WIDTH + 2) <= '0';
+               addr(DATA_ADDR_WIDTH + 3) <= '0';

        when OR_OP =>
                result_v := or_result;
        when OR_OP =>
                result_v := or_result;

-               addr(DATA_ADDR_WIDTH + 2) <= '0';
+               addr(DATA_ADDR_WIDTH + 3) <= '0';

        when XOR_OP =>
                result_v := xor_result;
        when XOR_OP =>
                result_v := xor_result;

-               addr(DATA_ADDR_WIDTH + 2) <= '0';
+               addr(DATA_ADDR_WIDTH + 3) <= '0';

        when SHIFT_OP =>
                result_v := shift_result;
        when SHIFT_OP =>
                result_v := shift_result;

-               addr(DATA_ADDR_WIDTH + 2) <= '0';
+               addr(DATA_ADDR_WIDTH + 3) <= '0';

    when LDST_OP =>
                 res_prod := '0';
                 mem_op := '1';
    when LDST_OP =>
                 res_prod := '0';
                 mem_op := '1';


@@ -155,7 +155,7 @@ begin
 
                         res_prod := '1';
                         mem_op := '0';
 
                         res_prod := '1';
                         mem_op := '0';

-                                                               addr(DATA_ADDR_WIDTH + 2) <= '0';
+                                                               addr(DATA_ADDR_WIDTH + 3) <= '0';

                 end if;
                 if op_detail(ST_OPT) = '1' then
                         mem_en := '1';
                 end if;
                 if op_detail(ST_OPT) = '1' then
                         mem_en := '1';

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index 2b711da003799afdb023292928077a6ec1b9f6b1..76bb94d2314eeae1dcefcad8141768edd294c008 100755 (executable)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -24,10 +24,10 @@ package common_pkg is
        constant REG_ZERO : gp_register_t := (others => '0');
 
        constant INSTR_ADDR_WIDTH       : INTEGER := 32;
        constant REG_ZERO : gp_register_t := (others => '0');
 
        constant INSTR_ADDR_WIDTH       : INTEGER := 32;

-       constant PHYS_INSTR_ADDR_WIDTH  : INTEGER := 11;
+       constant PHYS_INSTR_ADDR_WIDTH  : INTEGER := 10;

        constant ROM_INSTR_ADDR_WIDTH : INTEGER := 7;
        constant REG_ADDR_WIDTH         : INTEGER := 4;
        constant ROM_INSTR_ADDR_WIDTH : INTEGER := 7;
        constant REG_ADDR_WIDTH         : INTEGER := 4;

-       constant DATA_ADDR_WIDTH        : INTEGER := 11;
+       constant DATA_ADDR_WIDTH        : INTEGER := 10;

        constant PHYS_DATA_ADDR_WIDTH   : INTEGER := 32;
        
        constant NUM_OP_OPT_WIDTH       : INTEGER := 6;
        constant PHYS_DATA_ADDR_WIDTH   : INTEGER := 32;
        
        constant NUM_OP_OPT_WIDTH       : INTEGER := 6;


@@ -82,7 +82,7 @@ package common_pkg is
        constant UART_INT_EN_BIT : integer := 1;
        constant GLOBAL_INT_EN_BIT : integer := 0;
 
        constant UART_INT_EN_BIT : integer := 1;
        constant GLOBAL_INT_EN_BIT : integer := 0;
 

-       constant UART_INT_VECTOR : std_logic_vector(PHYS_INSTR_ADDR_WIDTH-1 downto 0) := "00000000001"; --integer := 1;
+       constant UART_INT_VECTOR : std_logic_vector(PHYS_INSTR_ADDR_WIDTH-1 downto 0) := (0 => '1', others => '0');

 
        type instruction_rec is record
 
 
        type instruction_rec is record
 

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 9731f37592de2f49322534d87c8968b0f6da25a3..8f24a135ef667ddd6388388fc5608c4f3d16ca7a 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -66,7 +66,7 @@ package core_pkg is
                --Data outputs
 --                     reg1_rd_data : out gp_register_t;
 --                     reg2_rd_data : out gp_register_t;
                --Data outputs
 --                     reg1_rd_data : out gp_register_t;
 --                     reg2_rd_data : out gp_register_t;

-                       branch_prediction_res : out instruction_word_t;
+                       branch_prediction_res : out instruction_addr_t;

                        branch_prediction_bit : out std_logic;
 
                        to_next_stage : out dec_op
                        branch_prediction_bit : out std_logic;
 
                        to_next_stage : out dec_op

diff --git a/cpu/src/decode_stage.vhd b/cpu/src/decode_stage.vhd
index 92f7bfcb557b5c693c51a4c7cb0bef1ef00f124f..620a2ccdbf048113e0b4c9b04187b052e19ba816 100644 (file)
--- a/cpu/src/decode_stage.vhd
+++ b/cpu/src/decode_stage.vhd
@@ -31,7 +31,7 @@ entity decode_stage is
                --Data outputs
 --                     reg1_rd_data : out gp_register_t;
 --                     reg2_rd_data : out gp_register_t;
                --Data outputs
 --                     reg1_rd_data : out gp_register_t;
 --                     reg2_rd_data : out gp_register_t;

-                       branch_prediction_res : out instruction_word_t;
+                       branch_prediction_res : out instruction_addr_t;

                        branch_prediction_bit : out std_logic;
 
                        to_next_stage : out dec_op
                        branch_prediction_bit : out std_logic;
 
                        to_next_stage : out dec_op

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index f86ad833a154e049e2d32fa3d79c5b5ef8c69f87..7e2032dde0c270bd01a0057de2d81dc28cbb1ac0 100644 (file)
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -81,8 +81,7 @@ begin
 
        if (instr_pc = x"0000007f" and rom_ram = ROM_USE) then
                rom_ram_nxt <= RAM_USE;
 
        if (instr_pc = x"0000007f" and rom_ram = ROM_USE) then
                rom_ram_nxt <= RAM_USE;

-               -- TODO: wenn genau auf adresse 0 im RAM ein br steht kracht es... :/
-               instr_r_addr_nxt <= x"00000000";
+               instr_r_addr_nxt <= (others => '0');

        end if;
 
        if (reset = RESET_VALUE) then
        end if;
 
        if (reset = RESET_VALUE) then


@@ -120,11 +119,11 @@ end process;
 out_logic : process (instr_r_addr, alu_jump_bit, int_req, jump_result)
 
 begin
 out_logic : process (instr_r_addr, alu_jump_bit, int_req, jump_result)
 
 begin

-       prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
-       prog_cnt(31 downto 11) <= (others => '0');
+       prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
+       prog_cnt(INSTR_ADDR_WIDTH-1 downto PHYS_INSTR_ADDR_WIDTH) <= (others => '0');

 
        if (int_req /= IDLE and alu_jump_bit = LOGIC_ACT ) then
 
        if (int_req /= IDLE and alu_jump_bit = LOGIC_ACT ) then

-               prog_cnt(10 downto 0) <= jump_result(10 downto 0);
+               prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= jump_result(PHYS_INSTR_ADDR_WIDTH-1 downto 0);

        end if;
 
 end process;
        end if;
 
 end process;

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index acf0f7db2032a88263d11df7b924e9aeac5450a5..6a3a4e6c0e11ef5b500e29f9ba24e5ed698d9c40 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -234,7 +234,7 @@ begin
        if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
                jump_addr <= data_ram_read;
        else
        if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
                jump_addr <= data_ram_read;
        else

-               jump_addr <= result;    
+               jump_addr <= result;

        end if;
 
 --     if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
        end if;
 
 --     if alu_jmp = '0' and br_pred = '1' and write_en = '0' then


@@ -269,7 +269,7 @@ begin
        data_addr <= (others => '0');
        dmem_we <= '0';
        
        data_addr <= (others => '0');
        dmem_we <= '0';
        

-       if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
+       if (wb_reg.address(DATA_ADDR_WIDTH+3) /= '1') then

                data_out := data_ram_read;
        else
                reg_we_v := reg_we_v and ext_anysel;
                data_out := data_ram_read;
        else
                reg_we_v := reg_we_v and ext_anysel;


@@ -306,7 +306,7 @@ begin
        
        data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); 
        
        
        data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); 
        

-       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
+       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+3) /= '1') then

                data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
                dmem_we <= wb_reg_nxt.dmem_write_en;
        end if;
                data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
                dmem_we <= wb_reg_nxt.dmem_write_en;
        end if;