spartan3e: BRAM gehaxe. lesbarer und wird auch richtig(er) instanziert

[calu.git] / cpu / src / ram_xilinx.vhd

diff --git a/cpu/src/ram_xilinx.vhd b/cpu/src/ram_xilinx.vhd
index 0166b55b3ed9b6b0bf693eada42b465835f97c6e..8e92507b2313e02dfe40b25c16b7fc526fc9279e 100644 (file)
--- a/cpu/src/ram_xilinx.vhd
+++ b/cpu/src/ram_xilinx.vhd
@@ -7,12 +7,20 @@ library UNISIM;
 use UNISIM.vcomponents.all;
 
 entity ram_xilinx is
-       generic ( ADDR_WIDTH : integer range 1 to integer'high);
-       port(clk : in std_logic;
-               addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-               be : in std_logic_vector(3 downto 0);
-               we : in std_logic; -- dummy :/
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               clk : in std_logic;
+
+               waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+               be : in std_logic_vector (3 downto 0);
+               
+               we : in std_logic;
+
                wdata : in std_logic_vector(31 downto 0);
+               
                q : out std_logic_vector(31 downto 0)
        );
 end;