X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=blobdiff_plain;f=cpu%2Fsrc%2Fram_xilinx.vhd;h=8e92507b2313e02dfe40b25c16b7fc526fc9279e;hp=0166b55b3ed9b6b0bf693eada42b465835f97c6e;hb=e10c1f8d87053aadfbd9d8ff1abb2219debe16d5;hpb=b663427fc426e8b7679534f8043b5530baf9cb17

diff --git a/cpu/src/ram_xilinx.vhd b/cpu/src/ram_xilinx.vhd
index 0166b55..8e92507 100644
--- a/cpu/src/ram_xilinx.vhd
+++ b/cpu/src/ram_xilinx.vhd
@@ -7,12 +7,20 @@ library UNISIM;
 use UNISIM.vcomponents.all;
 
 entity ram_xilinx is
-	generic	( ADDR_WIDTH : integer range 1 to integer'high);
-	port(clk : in std_logic;
-		addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-		be : in std_logic_vector(3 downto 0);
-		we : in std_logic; -- dummy :/
+	generic	(
+				ADDR_WIDTH : integer range 1 to integer'high
+			);
+	port(
+		clk : in std_logic;
+
+		waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+		be : in std_logic_vector (3 downto 0);
+		
+		we : in std_logic;
+
 		wdata : in std_logic_vector(31 downto 0);
+		
 		q : out std_logic_vector(31 downto 0)
 	);
 end;