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spartan3e: BRAM gehaxe. lesbarer und wird auch richtig(er) instanziert
authorBernhard Urban <lewurm@gmail.com>
Tue, 11 Jan 2011 01:10:32 +0000 (02:10 +0100)
committerBernhard Urban <lewurm@gmail.com>
Tue, 11 Jan 2011 01:10:32 +0000 (02:10 +0100)
cpu/src/mem_pkg.vhd patch | blob | history
cpu/src/ram_xilinx.vhd patch | blob | history
cpu/src/ram_xilinx_b.vhd patch | blob | history
cpu/src/writeback_stage_b.vhd patch | blob | history

diff --git a/cpu/src/mem_pkg.vhd b/cpu/src/mem_pkg.vhd
index c2d3cdd21c640bdbf32b0d4664684c01f9ba7b50..425af910287f0e10682f16532ddb9884f74f23b3 100644 (file)
--- a/cpu/src/mem_pkg.vhd
+++ b/cpu/src/mem_pkg.vhd
@@ -44,12 +44,20 @@ package mem_pkg is
        end component r_w_ram_be;
 
        component ram_xilinx is
-       generic ( ADDR_WIDTH : integer range 1 to integer'high);
-       port(clk : in std_logic;
-               addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-               be : in std_logic_vector(3 downto 0);
-               we : in std_logic; -- dummy :/
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               clk : in std_logic;
+
+               waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+               be : in std_logic_vector (3 downto 0);
+               
+               we : in std_logic;
+
                wdata : in std_logic_vector(31 downto 0);
+               
                q : out std_logic_vector(31 downto 0)
        );
        end component ram_xilinx;
diff --git a/cpu/src/ram_xilinx.vhd b/cpu/src/ram_xilinx.vhd
index 0166b55b3ed9b6b0bf693eada42b465835f97c6e..8e92507b2313e02dfe40b25c16b7fc526fc9279e 100644 (file)
--- a/cpu/src/ram_xilinx.vhd
+++ b/cpu/src/ram_xilinx.vhd
@@ -7,12 +7,20 @@ library UNISIM;
 use UNISIM.vcomponents.all;
 
 entity ram_xilinx is
-       generic ( ADDR_WIDTH : integer range 1 to integer'high);
-       port(clk : in std_logic;
-               addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-               be : in std_logic_vector(3 downto 0);
-               we : in std_logic; -- dummy :/
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               clk : in std_logic;
+
+               waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+               be : in std_logic_vector (3 downto 0);
+               
+               we : in std_logic;
+
                wdata : in std_logic_vector(31 downto 0);
+               
                q : out std_logic_vector(31 downto 0)
        );
 end;
diff --git a/cpu/src/ram_xilinx_b.vhd b/cpu/src/ram_xilinx_b.vhd
index a18b998c5dbb5784888a4c1af6bfa3b9aa0efae0..c9f5ab87b7dc1f5dcb077600c85b8f25552c93f5 100644 (file)
--- a/cpu/src/ram_xilinx_b.vhd
+++ b/cpu/src/ram_xilinx_b.vhd
@@ -1,321 +1,48 @@
 library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_misc.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-library UNISIM;
-use UNISIM.vcomponents.all;
 
-architecture logic of ram_xilinx is
-       constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
-       constant ONE : std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
-begin
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
 
-   RAMB16_S9_inst0 : RAMB16_S9 -- 2k x 8bit (+ 1 bit parity)
-   generic map (
-INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
-INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
-   port map (
-      DO   => q(31 downto 24),
-      DOP  => open, 
-      ADDR => addr(ADDR_WIDTH-1 downto 0),
-      CLK  => clk, 
-      DI   => wdata(31 downto 24),
-      DIP  => ZERO(0 downto 0),
-      EN   => ONE(0),
-      SSR  => ZERO(0),
-      WE   => be(3));
+use work.common_pkg.all;
+use work.mem_pkg.all;
 
-   RAMB16_S9_inst1 : RAMB16_S9
-   generic map (
-INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
-INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
-   port map (
-      DO   => q(23 downto 16),
-      DOP  => open, 
-      ADDR => addr(12 downto 2),
-      CLK  => clk, 
-      DI   => wdata(23 downto 16),
-      DIP  => ZERO(0 downto 0),
-      EN   => ONE(0),
-      SSR  => ZERO(0),
-      WE   => be(2));
+architecture behaviour of ram_xilinx is
+       type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
+       subtype stfu_t is std_logic_vector(BYTE_WIDTH-1 downto 0);
+       type ram_t is array (0 to (2**ADDR_WIDTH)-1) of stfu_t;
+       signal ram0 : ram_t := (others => x"00");
+       signal ram1 : ram_t := (others => x"00");
+       signal ram2 : ram_t := (others => x"00");
+       signal ram3 : ram_t := (others => x"00");
+       signal q_local : word_t;
 
-   RAMB16_S9_inst2 : RAMB16_S9
-   generic map (
-INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
-INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
-   port map (
-      DO   => q(15 downto 8),
-      DOP  => open, 
-      ADDR => addr(12 downto 2),
-      CLK  => clk, 
-      DI   => wdata(15 downto 8),
-      DIP  => ZERO(0 downto 0),
-      EN   => ONE(0),
-      SSR  => ZERO(0),
-      WE   => be(1));
+begin -- Re-organize the read data from the RAM to match the output
+       unpack: for i in 0 to 3 generate
+               q(8*(i+1) - 1 downto 8*i) <= q_local(i);
+       end generate unpack;
 
-   RAMB16_S9_inst3 : RAMB16_S9
-   generic map (
-INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
-INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
-INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
-   port map (
-      DO   => q(7 downto 0),
-      DOP  => open, 
-      ADDR => addr(12 downto 2),
-      CLK  => clk, 
-      DI   => wdata(7 downto 0),
-      DIP  => ZERO(0 downto 0),
-      EN   => ONE(0),
-      SSR  => ZERO(0),
-      WE   => be(0));
-end;
+       process(clk)
+       begin
+               if(rising_edge(clk)) then
+                       if(we = '1') then
+                               if(be(0) = '1') then
+                                       ram0(to_integer(UNSIGNED(waddr))) <= wdata(7 downto 0);
+                               end if;
+                               if be(1) = '1' then
+                                       ram1(to_integer(UNSIGNED(waddr))) <= wdata(15 downto 8);
+                               end if;
+                               if be(2) = '1' then
+                                       ram2(to_integer(UNSIGNED(waddr))) <= wdata(23 downto 16);
+                               end if;
+                               if be(3) = '1' then
+                                       ram3(to_integer(UNSIGNED(waddr))) <= wdata(31 downto 24);
+                               end if;
+                       end if;
+                       q_local(0) <= ram0(to_integer(UNSIGNED(raddr)));
+                       q_local(1) <= ram1(to_integer(UNSIGNED(raddr)));
+                       q_local(2) <= ram2(to_integer(UNSIGNED(raddr)));
+                       q_local(3) <= ram3(to_integer(UNSIGNED(raddr)));
+               end if;
+       end process;
+       
+end architecture behaviour;
diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index fd26a297b8e5727e9f5c2d975c600cb9b35115fd..a031207123e2836ec47551455ac1df7391623ae4 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -42,6 +42,7 @@ begin
                port map (
                        clk,
                        data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
                        wb_reg_nxt.byte_en,
                        dmem_we,
                        wb_reg_nxt.data, --ram_data,
Deep Thought (softcore CPU)