lustiger modelsim fix...

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index da886861d1cb98700e2b24352ef25f918ee7fca7..47406cab3f02f6b55dbf13bee70f23c3c9ab26a3 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -191,10 +191,11 @@ begin
        begin
                for i in 0 to 9 loop
                        rx_pin <= trans_data(i);
+                       report "bit: " & std_logic'image(trans_data(i));
                        dummy <= not dummy;
                        wait on dummy;
                        -- icwait(BAUD_COUNT);
-                       icwait(15);
+                       icwait(50);
                end loop;
        end txd;
 
@@ -204,6 +205,7 @@ begin
     -- initial reset
     -----------------------------------------------------------------------------
        sys_res_n_pin <= '0';
+       rx_pin <= '1';
 --     reg_w_addr_pin <= (others => '0');
 --     reg_wr_data_pin <= (others => '0');
 --     reg_we_pin <= '0';
@@ -215,9 +217,12 @@ begin
        
        icwait(10);
 
-       txd("0100000101");
+       txd("0000100101");
+       icwait(600);
+       icwait(600);
 
-       icwait(1000000000);
+       txd("0000100101");
+       icwait(600000000);
 
     ---------------------------------------------------------------------------
     -- exit testbench