timer: added as extension modul

[calu.git] / cpu / src / extension_pkg.vhd

diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd
index 20cf1cd02bce9d80f3444a7a7dace5baba84ccdd..f20a119af697a134d0e9484e4067fc00a1b4d554 100644 (file)
--- a/cpu/src/extension_pkg.vhd
+++ b/cpu/src/extension_pkg.vhd
@@ -21,7 +21,7 @@ subtype paddr_t is std_logic_vector(log2c(PCOUNT)-1 downto 0);
         type extmod_rec is record
                 sel   : std_logic;
                 wr_en : std_logic;
-                byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); 
+                byte_en : byte_en_t;
                 data : gp_register_t;
                 addr : ext_addr_t;     
         end record; 
@@ -34,15 +34,20 @@ type status_rec is record
                carry : std_logic;
 end record;
 
+procedure put_word_be (tmp : out gp_register_t; signal reg : in gp_register_t; signal byte_en : byte_en_t);
+
+-- Addressen der bis jetzt vorhanden extensions
+constant EXT_UART_ADDR:   ext_addrid_t := x"0000200";
 constant EXT_7SEG_ADDR:   ext_addrid_t := x"0000201";
+constant EXT_INT_ADDR:   ext_addrid_t := x"0000202";
+constant EXT_IMP_ADDR:   ext_addrid_t := x"0000203";
+constant EXT_TIMER_ADDR:  ext_addrid_t := x"0000204";
+-- dummy addressen
 constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB";
-constant EXT_TIMER_ADDR:  ext_addrid_t := x"FFFFFFC";
 constant EXT_AC97_ADDR:   ext_addrid_t := x"FFFFFFD";
--- constant EXT_UART_ADDR:   ext_addrid_t := x"FFFFFFE";
-constant EXT_UART_ADDR:   ext_addrid_t := x"0000200";
 constant EXT_GPMP_ADDR:    ext_addrid_t := x"FFFFFFF";
 
- component extension_gpm is
+component extension_gpm is
         --some modules won't need all inputs/outputs
        generic (
                        -- active reset value
@@ -67,6 +72,36 @@ constant EXT_GPMP_ADDR:    ext_addrid_t := x"FFFFFFF";
                );
  end component extension_gpm;
 
+component extension_interrupt is
+        --some modules won't need all inputs/outputs
+       generic (
+                       -- active reset value
+                       RESET_VALUE : std_logic
+                       );
+       port(
+               --System inputs
+                       clk :   in std_logic;
+                       reset : in std_logic;
+               -- general extension interface                  
+                       ext_reg  : in extmod_rec;
+                       data_out : out gp_register_t;
+               -- Input
+                       uart_int : in std_logic;
+               -- Ouput
+                       int_req : out interrupt_t
+               );
+ end component extension_interrupt;
 
 
 end package extension_pkg;
+
+package body extension_pkg is
+       procedure put_word_be (tmp : out gp_register_t; signal reg : in gp_register_t; signal byte_en : byte_en_t) is
+       begin
+               for i in 0 to 3 loop
+                       if byte_en(i) = '1' then
+                               tmp(((i+1)*byte_t'length-1) downto i*byte_t'length) := reg(((i+1)*byte_t'length-1) downto i*byte_t'length);
+                       end if;
+               end loop;
+       end;
+end package body extension_pkg;