timer: added as extension modul

diff --git a/cpu/sim/.gitignore b/cpu/sim/.gitignore
index 891db2f220f27c2634c0b48a4098a57d37a4c596..2245470c01d10dc4098ceb55545915f62ceb1b76 100644 (file)
--- a/cpu/sim/.gitignore
+++ b/cpu/sim/.gitignore
@@ -1,3 +1,4 @@
 *.ini
 *.wlf
+*.nfs*
 /work/*

diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do
index f2e2b79dabcb364f87f1a505f8b6ab04c00e8467..07def81a9009c77c72bd2fa99fb4f176eba568bb 100644 (file)
--- a/cpu/sim/testcore1.do
+++ b/cpu/sim/testcore1.do
@@ -49,6 +49,10 @@ vcom -work work ../src/extension_7seg_pkg.vhd
 vcom -work work ../src/extension_7seg.vhd
 vcom -work work ../src/extension_7seg_b.vhd
 
+vcom -work work ../src/extension_timer_pkg.vhd
+vcom -work work ../src/extension_timer.vhd
+vcom -work work ../src/extension_timer_b.vhd
+
 vcom -work work ../src/extension_uart_pkg.vhd
 vcom -work work ../src/rs232_tx.vhd
 vcom -work work ../src/rs232_tx_arc.vhd
@@ -144,6 +148,11 @@ add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/uart_dat
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg.sel
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_rx_inst/rx_data_nxt
 
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w1_st_co
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w1_st_co_nxt
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w2_im_val
+add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w2_im_val_nxt
+
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/reg_we
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/write_en
 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_en

diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd
index 907628385986da88e732f5702701db725f0264ec..f20a119af697a134d0e9484e4067fc00a1b4d554 100644 (file)
--- a/cpu/src/extension_pkg.vhd
+++ b/cpu/src/extension_pkg.vhd
@@ -34,15 +34,16 @@ type status_rec is record
                carry : std_logic;
 end record;
 
+procedure put_word_be (tmp : out gp_register_t; signal reg : in gp_register_t; signal byte_en : byte_en_t);
 
 -- Addressen der bis jetzt vorhanden extensions
 constant EXT_UART_ADDR:   ext_addrid_t := x"0000200";
 constant EXT_7SEG_ADDR:   ext_addrid_t := x"0000201";
 constant EXT_INT_ADDR:   ext_addrid_t := x"0000202";
 constant EXT_IMP_ADDR:   ext_addrid_t := x"0000203";
+constant EXT_TIMER_ADDR:  ext_addrid_t := x"0000204";
 -- dummy addressen
 constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB";
-constant EXT_TIMER_ADDR:  ext_addrid_t := x"FFFFFFC";
 constant EXT_AC97_ADDR:   ext_addrid_t := x"FFFFFFD";
 constant EXT_GPMP_ADDR:    ext_addrid_t := x"FFFFFFF";
 
@@ -93,3 +94,14 @@ component extension_interrupt is
 
 
 end package extension_pkg;
+
+package body extension_pkg is
+       procedure put_word_be (tmp : out gp_register_t; signal reg : in gp_register_t; signal byte_en : byte_en_t) is
+       begin
+               for i in 0 to 3 loop
+                       if byte_en(i) = '1' then
+                               tmp(((i+1)*byte_t'length-1) downto i*byte_t'length) := reg(((i+1)*byte_t'length-1) downto i*byte_t'length);
+                       end if;
+               end loop;
+       end;
+end package body extension_pkg;

diff --git a/cpu/src/extension_timer.vhd b/cpu/src/extension_timer.vhd
new file mode 100644 (file)
index 0000000..56843a2
--- /dev/null
+++ b/cpu/src/extension_timer.vhd
@@ -0,0 +1,19 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_pkg.all;
+use work.extension_imp_pkg.all;
+
+entity extension_timer is
+       generic ( RESET_VALUE : std_logic);
+       port(
+                       --System inputs
+                       clk :   in std_logic;
+                       reset : in std_logic;
+                       -- general extension interface
+                       ext_reg  : in extmod_rec;
+                       data_out : out gp_register_t
+               );
+end extension_timer;

diff --git a/cpu/src/extension_timer_b.vhd b/cpu/src/extension_timer_b.vhd
new file mode 100644 (file)
index 0000000..6ceb8de
--- /dev/null
+++ b/cpu/src/extension_timer_b.vhd
@@ -0,0 +1,95 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+
+
+use work.mem_pkg.all;
+use work.extension_pkg.all;
+use work.extension_timer_pkg.all;
+
+architecture behav of extension_timer is
+
+signal w1_st_co, w1_st_co_nxt, w2_im_val, w2_im_val_nxt : gp_register_t;
+signal w3_im_notused, w3_im_notused_nxt, w4_im_notused, w4_im_notused_nxt : gp_register_t;
+
+begin
+
+syn : process (clk, reset)
+begin
+   if (reset = RESET_VALUE) then
+                       w1_st_co <= (others => '0');
+                       w2_im_val <= (others => '0');
+                       w3_im_notused <= (others => '0');
+                       w4_im_notused <= (others => '0');
+       elsif rising_edge(clk) then
+                       w1_st_co <= w1_st_co_nxt;
+                       w2_im_val <= w2_im_val_nxt;
+                       w3_im_notused <= w3_im_notused_nxt;
+                       w4_im_notused <= w4_im_notused_nxt;
+   end if;
+end process syn;
+
+-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
+
+gwriten : process (ext_reg, w1_st_co, w2_im_val, w3_im_notused, w4_im_notused)
+variable tmp_data : gp_register_t;
+begin
+       w1_st_co_nxt <= w1_st_co;
+       w2_im_val_nxt <= w2_im_val;
+       w3_im_notused_nxt <= w3_im_notused;
+       w4_im_notused_nxt <= w4_im_notused;
+
+       -- timer logic
+       if (w1_st_co(0) = '1') then -- timer enabled?
+               w2_im_val_nxt <= std_logic_vector(IEEE.numeric_std.unsigned(w2_im_val) + 1);
+               -- n00b overflow (logic elements sparen...)
+               if(w2_im_val(31) = '1') then 
+                       w1_st_co_nxt(16) <= '1';
+               end if;
+       end if;
+
+       if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
+               tmp_data := (others =>'0');                     
+               for i in 0 to 3 loop
+                       if ext_reg.byte_en(i) = '1' then
+                               tmp_data(((i+1)*byte_t'length-1) downto i*byte_t'length) := ext_reg.data(((i+1)*byte_t'length-1) downto i*byte_t'length);
+                       end if;
+               end loop;
+
+               case ext_reg.addr(1 downto 0) is
+               when "00" => -- status/config
+                       w1_st_co_nxt <= tmp_data;
+               when "01" => -- timer value
+                       w2_im_val_nxt <= tmp_data;
+               when "10" => null;
+               when "11" => null;
+               when others => null;
+               end case;
+       end if;
+end process gwriten;
+
+gread : process (clk, ext_reg, w1_st_co, w2_im_val, w3_im_notused, w4_im_notused)
+variable tmp_data : gp_register_t;
+begin
+       tmp_data := (others => '0');
+       if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
+               case ext_reg.addr(1 downto 0) is
+               when "00" => put_word_be(tmp_data, w1_st_co, ext_reg.byte_en);
+               when "01" => put_word_be(tmp_data, w2_im_val, ext_reg.byte_en);
+               when "10" => put_word_be(tmp_data, w3_im_notused, ext_reg.byte_en);
+               when "11" => put_word_be(tmp_data, w4_im_notused, ext_reg.byte_en);
+               when others => null;
+               end case;
+       end if;
+       data_out <= tmp_data;
+end process gread;
+
+-------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
+-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
+-------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
+end behav;

diff --git a/cpu/src/extension_timer_pkg.vhd b/cpu/src/extension_timer_pkg.vhd
new file mode 100644 (file)
index 0000000..c2d7250
--- /dev/null
+++ b/cpu/src/extension_timer_pkg.vhd
@@ -0,0 +1,21 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_pkg.all;
+
+package extension_timer_pkg is
+       component extension_timer is
+       generic ( RESET_VALUE : std_logic);
+       port(
+                       --System inputs
+                       clk :   in std_logic;
+                       reset : in std_logic;
+                       -- general extension interface
+                       ext_reg  : in extmod_rec;
+                       data_out : out gp_register_t
+               );
+       end component extension_timer;
+end package extension_timer_pkg;

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index eda81023058f86351b0850bded6ddccc83fd102a..8193ab49c19674c1fce65fbd0be0fe296509de61 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -92,7 +92,7 @@ begin
                --System inputs
                        clk => sys_clk_pin, --: in std_logic;
                        reset => sys_res_n_pin, --: in std_logic;
-                       s_reset => '0',
+                       s_reset => '1',
                --Data inputs
                        jump_result => jump_result_pin, --: in instruction_addr_t;
                        prediction_result => prediction_result_pin, --: in instruction_addr_t;

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 78a17a451984710d71b39cd511b66c135d9e9903..83084c814fd385f8bdc1e32b2c9fda2ba67f921d 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -10,6 +10,7 @@ use work.extension_pkg.all;
 use work.extension_uart_pkg.all;
 use work.extension_7seg_pkg.all;
 use work.extension_imp_pkg.all;
+use work.extension_timer_pkg.all;
 
 architecture behav of writeback_stage is
 
@@ -30,8 +31,6 @@ signal sel_nxt, dmem_we, ext_anysel : std_logic;
 signal calc_mem_res : gp_register_t;
 
 begin
-
-       ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
        ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
 
        spartan3e: if FPGATYPE = "s3e" generate
@@ -127,6 +126,10 @@ interrupt : extension_interrupt
                int_req
 
                );
+
+timer : extension_timer
+       generic map(RESET_VALUE)
+       port map(clk, reset, ext_timer, ext_timer_out);
        
 syn: process(clk, reset)
 

diff --git a/dt/dt.qsf b/dt/dt.qsf
index 8180379336117b0e8aa89b6619640e10d772c6cb..289cb313f4b154ed6096fde97d422a557e58bb41 100644 (file)
--- a/dt/dt.qsf
+++ b/dt/dt.qsf
@@ -112,9 +112,11 @@ set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp_pkg.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp.vhd
-set_global_assignment -name VHDL_FILE ../cpu/src/extension_interrupt_pkg.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_interrupt_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_interrupt.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_timer_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_timer_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_timer.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_pkg.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension.vhd
@@ -138,4 +140,6 @@ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
 set_location_assignment PIN_41 -to soft_res
 set_global_assignment -name MISC_FILE /homes/c0725782/calu/dt/dt.dpf
+
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

diff --git a/progs/testbench.s b/progs/testbench.s
index 624e3c9312a734d0474f088e4b3e6a1d5f9c07da..b98784cf63796e6ff563405fe50d7bd388b1dd53 100644 (file)
--- a/progs/testbench.s
+++ b/progs/testbench.s
@@ -1,15 +1,9 @@
 #include "dt_inc.s"
-
-.data
-.org 0x0
-list:
-       .fill 0x1 ;1. element = 1 ;0x10
-       .fill 0x1 ;2. element = 1 ;0x14
-       .fill 0x10, 0x0 ;nullen..
-str:
-       .ascii "hier das ergebnis: "
 .text
 .org 0x0
+       .define TIMER_BASE, 0x2040
+       .define T_STCFG, 0x0
+       .define T_VAL, 0x4
 start:
        br+ main
        br+ main
@@ -21,22 +15,23 @@ main:
 
        ldis r1, 0x42
        call u_send_byte
-       
-       ldis r0, bla/4
-       ; addi r1, r0, 0
-       ; call u_send_byte
-       brr r0
 
-       ldis r1, 0x43
-       call u_send_byte
+       ldis r11, TIMER_BASE@lo
+       ldih r11, TIMER_BASE@hi
 
-hang:
-       br hang
+       ldis r1, 0x1
+       stw r1, T_STCFG(r11)
 
+loop:
+       call u_recv_byte
+       cmpi r0, 0x42
+       breq bla
+       ldw r1, T_VAL(r11)
+       call u_send_uint
+       call u_send_newline
+       br loop
 
-.org 0x50
 bla:
-       call u_init
-       ldis r1, 0x41
-       call u_send_byte
-       br hang
+       ldis r1, 0
+       stw r1, T_VAL(r11)
+       br loop