isa: assigned opcodes

[calu.git] / 2_isa / logic.ptex

diff --git a/2_isa/logic.ptex b/2_isa/logic.ptex
index aa97db88f7332c1f34d43d9f5b375455e5d79ba5..58fa987bcf884b007649de6662908dedea4f07c1 100644 (file)
--- a/2_isa/logic.ptex
+++ b/2_isa/logic.ptex
@@ -1,25 +1,32 @@
 
 
-ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
+ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 10 | 1',
+'Conditions | OpCode (00100) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
 
 # ins ('32', 'andi', 'And im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D');
+ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
+'Conditions | OpCode (00101) | Register Destination| Immediate | H/L | F | D');
 
-ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | D');
+ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1',
+'Conditions | OpCode (00110) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
 
 # ins ('32', 'ori', 'Or im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D');
+ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
+'Conditions | OpCode (00111) | Register Destination| Immediate | H/L | F | D');
 
-ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | D');
+ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1',
+'Conditions | OpCode (01001) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
 
 # ins ('32', 'xori', 'Xor im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D',
+ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
+'Conditions | OpCode (01010) | Register Destination| Immediate | H/L | F | D',
 '', '', '', 'not rD - xorxlf rD, rD, 0xFFFF');
 
-ins ('32', 'l{l,r}s', 'left/right shift', '4 | 5 | 4 | 4 | 5 | 6 | 1 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | l/r | A C | D',
+ins ('32', 'l{l,r}s', 'left/right shift', '4 | 5 | 4 | 4 | 5 | 6 | 1 | 1 | 1 | 1',
+'Conditions | OpCode (01011) | Register Destination|Register A (Source1)| Immediate | - | l/r | A C | D',
 '',' | Will change if C is set | | ');
 
 #plaintext ('\\mbox{}\\\\ \\todo{lls und lrs zusammenfassen $\rightarrow$ ein bit entscheidet fuer shift nach links oder rechts}');