ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 10 | 1',
'Conditions | OpCode (00100) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');

# ins ('32', 'andi', 'And im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');

ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
'Conditions | OpCode (00101) | Register Destination| Immediate | H/L | F | D');

ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1',
'Conditions | OpCode (00110) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');

# ins ('32', 'ori', 'Or im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');

ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
'Conditions | OpCode (00111) | Register Destination| Immediate | H/L | F | D');

ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1',
'Conditions | OpCode (01001) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');

# ins ('32', 'xori', 'Xor im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');

ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
'Conditions | OpCode (01010) | Register Destination| Immediate | H/L | F | D',
'', '', '', 'not rD - xorxlf rD, rD, 0xFFFF');

ins ('32', 'l{l,r}s', 'left/right shift', '4 | 5 | 4 | 4 | 5 | 6 | 1 | 1 | 1 | 1',
'Conditions | OpCode (01011) | Register Destination|Register A (Source1)| Immediate | - | l/r | A C | D',
'',' | Will change if C is set | | ');

#plaintext ('\\mbox{}\\\\ \\todo{lls und lrs zusammenfassen $\rightarrow$ ein bit entscheidet fuer shift nach links oder rechts}');

# ins ('32', 'lrs', 'right shift', '4 | 5 | 4 | 4 | 5 | 7 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | A | C | D',
# '',' | Will change if C is set | | ');