isa: assigned opcodes

by int rand() { return 4; }

diff --git a/2_isa/arith.ptex b/2_isa/arith.ptex
index 7d1d1b36751bfc01e3d2b6d5692334ba725c530a..32bd6f40b5d518bbc2888911e59916d78e29e39d 100644 (file)
--- a/2_isa/arith.ptex
+++ b/2_isa/arith.ptex
@@ -1,21 +1,21 @@
 ins ('32', 'add', 'Add',
 '4 | 5 | 4 | 4 | 4 | 9 | 1 | 1',
-'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C | D',
+'Conditions | OpCode (00000) | Register Destination|Register A (Source1)| Register B (Source2) | - | C | D',
 'Adds register A and register B and saves the result in register Destination',
 'is set to the MSB of the result | is set if addition has a carry out | is set if a overflow occurred | is set if the result is zero ',
 'add  r0, r2, r4 ; add low bytes
  addc r1, r3, r5 ; add high bytes');
 
-ins ('32', 'addi', 'Add im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | S | C | D',
+ins ('32', 'addi', 'Add im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode (00010) | Register Destination|Register A (Source1)| Immediate | S | C | D',
 'Adds register A and immediate and saves the result in register Destination',
 '','',
 'mov rD, rS - addid rD, rS, 0');
 
 # ins ('32', 'addx', 'Add im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
 
-ins ('32', 'sub', 'Sub', '4 | 5 | 4 | 4 | 4 | 9 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C | D');
+ins ('32', 'sub', 'Sub', '4 | 5 | 4 | 4 | 4 | 9 | 1 | 1', 'Conditions | OpCode (00001) | Register Destination|Register A (Source1)| Register B (Source2) | - | C | D');
 
-ins ('32', 'subi', 'Sub im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | S | C | D');
+ins ('32', 'subi', 'Sub im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode (00011) | Register Destination|Register A (Source1)| Immediate | S | C | D');
 
 # ins ('32', 'subx', 'Sub im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
 

diff --git a/2_isa/data.ptex b/2_isa/data.ptex
index f765a2d4a93b5851d078fe4a758f06c7624c81ac..bd2e5069e0029c6a4ab88433b264e3e8da60db24 100644 (file)
--- a/2_isa/data.ptex
+++ b/2_isa/data.ptex
@@ -1,24 +1,5 @@
-ins ('32', 'mov\{p,s\}f', 'Move from PSW/Stack', '4 | 5 | 4 | 1 | 18', 'Conditions | OpCode | Register Destination| st | - ');
-
-ins ('32', 'mov\{p,s\}t', 'Move to PSW/Stack', '4 | 5 | 4 | 1 | 18', 'Conditions | OpCode | Register Source | st | - ',
-'This instruction will set PSW or Stack to the value stored in the source register. When the move is to PSW the flags will be set like they are set in the source register.');
-
-ins ('32', 'ldw', 'Load word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
-ins ('32', 'ldh', 'Load half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
-ins ('32', 'ldb', 'Load byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement');
-
-ins ('32', 'ldi', 'Load immediate', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | S | h/l | - ');
-
-ins ('32', 'stw', 'store word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
-ins ('32', 'sth', 'store half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
-ins ('32', 'stb', 'store byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
-
-ins ('32', 'ldx', 'Load from program space', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
-
-ins ('32', 'stx', 'Store to program space', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
-
-
-ins ('32', 'stackop', 'pop/push/disc/fetch from/to stack', '4 | 5 | 4 | 2 | 17', 'Conditions | OpCode | Register Destination (not for disc) | Type | - ',
+ins ('32', 'stackop', 'pop/push/disc/fetch from/to stack', '4 | 5 | 4 | 2 | 17',
+'Conditions | OpCode (01011) | Register Destination (not for disc) | Type | - ',
 'This operation should not be used direct, instead the aliases pop, push, disc and fetch should be used.
 \\begin{table}[!h]
 \\centering
@@ -38,3 +19,34 @@ ins ('32', 'stackop', 'pop/push/disc/fetch from/to stack', '4 | 5 | 4 | 2 | 17',
 #ins ('32', 'disc', 'discard top-element from stack', '4 | 5 |  23', 'Conditions | OpCode | - ');
 
 #ins ('32', 'fetch', 'get top-element from stack', '4 | 5 | 4 |  19', 'Conditions | OpCode | Register Destination | - ');
+
+
+ins ('32', 'mov\{p,s\}f', 'Move from PSW/Stack', '4 | 5 | 4 | 1 | 18',
+'Conditions | OpCode (01100) | Register Destination| st | - ');
+
+ins ('32', 'mov\{p,s\}t', 'Move to PSW/Stack', '4 | 5 | 4 | 1 | 18',
+'Conditions | OpCode (01101) | Register Source | st | - ',
+'This instruction will set PSW or Stack to the value stored in the source register. When the move is to PSW the flags will be set like they are set in the source register.');
+
+ins ('32', 'ldw', 'Load word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15',
+'Conditions | OpCode (01110) | Register Destination|Register Address| displacement ');
+ins ('32', 'ldh', 'Load half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15',
+'Conditions | OpCode (10000) | Register Destination|Register Address| displacement ');
+ins ('32', 'ldb', 'Load byte, 8bit', '4 | 5 | 4 | 4 | 15',
+'Conditions | OpCode (10010) | Register Destination|Register Address| displacement');
+
+ins ('32', 'ldi', 'Load immediate', '4 | 5 | 4 | 16 | 1 | 1 | 1',
+'Conditions | OpCode (11010) | Register Destination| Immediate | S | h/l | - ');
+
+ins ('32', 'stw', 'store word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15',
+'Conditions | OpCode (01111) | Register Destination|Register Address| displacement ');
+ins ('32', 'sth', 'store half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15',
+'Conditions | OpCode (10001) | Register Destination|Register Address| displacement ');
+ins ('32', 'stb', 'store byte, 8bit', '4 | 5 | 4 | 4 | 15',
+'Conditions | OpCode (10011) | Register Destination|Register Address| displacement ');
+
+ins ('32', 'ldx', 'Load from program space', '4 | 5 | 4 | 4 | 15',
+'Conditions | OpCode (10100) | Register Destination|Register Address| displacement ');
+
+ins ('32', 'stx', 'Store to program space', '4 | 5 | 4 | 4 | 15',
+'Conditions | OpCode (10101) | Register Destination|Register Address| displacement ');

diff --git a/2_isa/logic.ptex b/2_isa/logic.ptex
index aa97db88f7332c1f34d43d9f5b375455e5d79ba5..58fa987bcf884b007649de6662908dedea4f07c1 100644 (file)
--- a/2_isa/logic.ptex
+++ b/2_isa/logic.ptex
@@ -1,25 +1,32 @@
 
 
-ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
+ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 10 | 1',
+'Conditions | OpCode (00100) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
 
 # ins ('32', 'andi', 'And im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D');
+ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
+'Conditions | OpCode (00101) | Register Destination| Immediate | H/L | F | D');
 
-ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | D');
+ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1',
+'Conditions | OpCode (00110) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
 
 # ins ('32', 'ori', 'Or im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D');
+ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
+'Conditions | OpCode (00111) | Register Destination| Immediate | H/L | F | D');
 
-ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | D');
+ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1',
+'Conditions | OpCode (01001) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
 
 # ins ('32', 'xori', 'Xor im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D',
+ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
+'Conditions | OpCode (01010) | Register Destination| Immediate | H/L | F | D',
 '', '', '', 'not rD - xorxlf rD, rD, 0xFFFF');
 
-ins ('32', 'l{l,r}s', 'left/right shift', '4 | 5 | 4 | 4 | 5 | 6 | 1 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | l/r | A C | D',
+ins ('32', 'l{l,r}s', 'left/right shift', '4 | 5 | 4 | 4 | 5 | 6 | 1 | 1 | 1 | 1',
+'Conditions | OpCode (01011) | Register Destination|Register A (Source1)| Immediate | - | l/r | A C | D',
 '',' | Will change if C is set | | ');
 
 #plaintext ('\\mbox{}\\\\ \\todo{lls und lrs zusammenfassen $\rightarrow$ ein bit entscheidet fuer shift nach links oder rechts}');

diff --git a/2_isa/misc.ptex b/2_isa/misc.ptex
index 775d8fb6e080bc1e01eecb69a282a5d61d062d45..a36bf55145b4525cac43f2b52901cc566f0be7ea 100644 (file)
--- a/2_isa/misc.ptex
+++ b/2_isa/misc.ptex
@@ -1,4 +1,5 @@
-ins ('32', 'branch', 'Branch; jump to pc+imm', '4 | 5 | 16 | 3 | 2 | 1 | 1', 'Conditions | OpCode | Immediate | - | Type | +/- | S',
+ins ('32', 'branch', 'Branch; jump to pc+imm', '4 | 5 | 16 | 3 | 2 | 1 | 1',
+'Conditions | OpCode (10110) | Immediate | - | Type | +/- | S',
 'This instruction should be used with it\'s aliases branch, call, ret and reti. No flags will be affected by this instructions.
 \\begin{table}[!h]
 \\centering
@@ -11,7 +12,8 @@ ins ('32', 'branch', 'Branch; jump to pc+imm', '4 | 5 | 16 | 3 | 2 | 1 | 1', 'Co
 \\end{tabular}
 \\end{table}');
 
-ins ('32', 'branchreg', 'Branch; jump to value of reg', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register A | - | Type | +/- | -',
+ins ('32', 'branchreg', 'Branch; jump to value of reg', '4 | 5 | 4 | 16 | 1 | 1 | 1',
+'Conditions | OpCode (10111) | Register A | - | Type | +/- | -',
 'This instruction should be used with it\'s aliases branchr and callr. No flags will be affected by this instructions. If Type is set to 1, the current value of the programcounter is pushed onto the stack.');
 
 #ins ('32', 'call', 'Call; save pc+4 in stack, jump to pc+imm', '4 | 5 | 16 | 5 | 1 | 1', 'Conditions | OpCode | Immediate | - | +/- | S');
@@ -24,11 +26,12 @@ ins ('32', 'branchreg', 'Branch; jump to value of reg', '4 | 5 | 4 | 16 | 1 | 1
 
 #ins ('32', 'reti', 'reti', '4 | 5 | 23 ', 'Conditions | OpCode | -');
 
-ins ('32', 'cmp', 'compare (rS1 - rS2)', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register A (Source1) | Register B (Source2) | -',
+ins ('32', 'cmp', 'compare (rS1 - rS2)', '4 | 5 | 4 | 4 | 15',
+'Conditions | OpCode (11000) | Register A (Source1) | Register B (Source2) | -',
 'This instructions compares the two source registers by subtraction of register B from register A and setting the flags accordingly',
 'is set to the MSB of the result|is set if the subtraction has a carry out|is set if an overflow occurred|is set if the result is zero');
 
-ins ('32', 'cmpi', 'compare (rS1 - imm)', '4 | 5 |  4 | 16 | 3', 'Conditions | OpCode | Register A (Source1) | Immediate | -',
+ins ('32', 'cmpi', 'compare (rS1 - imm)', '4 | 5 |  4 | 16 | 3',
+'Conditions | OpCode (11001) | Register A (Source1) | Immediate | -',
 'This instructions compares the the source register with the immediate be subtracting the immediate from register A and setting the flags accordingly',
 'is set to the MSB of the result|is set if the subtraction has a carry out|is set if an overflow occurred|is set if the result is zero');
-