2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
10 architecture behav of writeback_stage is
13 signal data_ram_read : word_t;
15 signal wb_reg, wb_reg_nxt : writeback_rec;
28 wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
29 wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
30 wb_reg_nxt.dmem_write_en,
36 syn: process(clk, reset)
40 if (reset = RESET_VALUE) then
41 wb_reg.address <= (others => '0');
42 wb_reg.dmem_en <= '0';
43 wb_reg.dmem_write_en <= '0';
46 elsif rising_edge(clk) then
52 -- type writeback_rec is record
53 -- address : in word_t; --ureg
54 -- dmem_en : in std_logic; --ureg (jump addr in mem or in address)
55 -- dmem_write_en : in std_logic; --ureg
56 -- hword_hl : in std_logic --ureg
61 shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred)
64 wb_reg_nxt.address <= address;
65 wb_reg_nxt.dmem_en <= dmem_en;
66 wb_reg_nxt.dmem_write_en <= dmem_write_en;
67 wb_reg_nxt.hword <= hword;
68 wb_reg_nxt.byte_s <= byte_s;
70 regfile_val <= result; --(others => '0');
72 if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and
73 regfile_val <= data_ram_read;
74 if (wb_reg.hword = '1') then
75 regfile_val <= (others => '0');
76 if (wb_reg.address(1) = '1') then
77 regfile_val(15 downto 0) <= data_ram_read(31 downto 16);
79 regfile_val(15 downto 0) <= data_ram_read(15 downto 0);
82 if (wb_reg.byte_s = '1') then
83 regfile_val <= (others => '0');
84 case wb_reg.address(1 downto 0) is
85 when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0);
86 when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
87 when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
88 when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
94 jump <= alu_jmp xor br_pred;
96 if ((alu_jmp and wb_reg.dmem_en) = '1') then
97 jump_addr <= data_ram_read;
102 -- result : in gp_register_t; --reg (alu result or jumpaddr)
103 -- result_addr : in gp_addr_t; --reg
104 -- address : in word_t; --ureg
105 -- alu_jmp : in std_logic; --reg
106 -- br_pred : in std_logic; --reg
107 -- write_en : in std_logic; --reg (register file)
108 -- dmem_en : in std_logic; --ureg (jump addr in mem or in result)
109 -- dmem_write_en : in std_logic; --ureg
110 -- hword : in std_logic --ureg
114 out_logic: process(write_en, result_addr, wb_reg, alu_jmp)
117 reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
118 reg_addr <= result_addr;