2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
7 architecture behav of writeback_stage is
12 signal data_ram_read : word_t;
14 signal wb_reg, wb_reg_nxt : writeback_rec;
24 wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
25 wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
26 wb_reg_nxt.dmem_write_en,
32 syn: process(sys_clk, reset)
36 if (reset = RESET_VALUE) then
37 wb_reg_nxt.address <= (others => '0');
38 wb_reg_nxt.dmem_en <= '0';
39 wb_reg_nxt.dmem_write_en <= '0';
40 wb_reg_nxt.hword <= '0';
41 wb_reg_nxt.byte_s <= '0';
42 elsif rising_edge(sys_clk) then
48 -- type writeback_rec is record
49 -- address : in word_t; --ureg
50 -- dmem_en : in std_logic; --ureg (jump addr in mem or in address)
51 -- dmem_write_en : in std_logic; --ureg
52 -- hword_hl : in std_logic --ureg
57 shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword_hl, wb_reg, result)
60 wb_reg_nxt.address <= address;
61 wb_reg_nxt.dmem_en <= dmem_en;
62 wb_reg_nxt.dmem_write_en <= dmem_write_en;
63 wb_reg_nxt.hword <= hword;
64 wb_reg_nxt.byte_s <= byte_s;
66 regfile_val <= result; --(others => '0');
68 if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and
69 regfile_val <= data_ram_read;
70 if (wb_reg.hword = '1') then
71 regfile_val <= (others => '0');
72 if (wb_reg.address(1) = '1') then
73 regfile_val(15 downto 0) <= data_ram_read(31 downto 16);
75 regfile_val(15 downto 0) <= data_ram_read(15 downto 0);
78 if (wb_reg.byte_s = '1') then
79 regfile_val <= (others => '0');
80 case wb_reg.address(1 downto 0) is
81 when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0);
82 when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
83 when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
84 when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
89 jump <= alu_jmp xor br_pred;
91 if ((alu_jmp and wb_reg.dmem_en) = '1') then
92 jump_addr <= data_ram_read;
97 -- result : in gp_register_t; --reg (alu result or jumpaddr)
98 -- result_addr : in gp_addr_t; --reg
99 -- address : in word_t; --ureg
100 -- alu_jmp : in std_logic; --reg
101 -- br_pred : in std_logic; --reg
102 -- write_en : in std_logic; --reg (register file)
103 -- dmem_en : in std_logic; --ureg (jump addr in mem or in result)
104 -- dmem_write_en : in std_logic; --ureg
105 -- hword : in std_logic --ureg
109 out_logic: process(write_en, result_addr)
113 reg_addr <= result_addr;