library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.core_pkg.all;

architecture behav of writeback_stage is


begin

signal data_ram_read : word_t;

signal wb_reg, wb_reg_nxt : writeback_rec;

	data_ram : r_w_ram
		generic map (
			PHYS_DATA_ADDR_WIDTH,
			WORD_WIDTH
		)
		
		port map (
			clk,
			wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
			wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
			wb_reg_nxt.dmem_write_en,
			ram_data,
			data_ram_read
		);


syn: process(sys_clk, reset)

begin

	if (reset = RESET_VALUE) then
		wb_reg_nxt.address <= (others => '0');
		wb_reg_nxt.dmem_en <= '0';
		wb_reg_nxt.dmem_write_en <= '0';
		wb_reg_nxt.hword <= '0';
		wb_reg_nxt.byte_s <= '0';
	elsif rising_edge(sys_clk) then
		wb_reg <= wb_reg_nxt;
	end if;
	
end process; 

--	type writeback_rec is record
--		address : in word_t;		--ureg 
--		dmem_en : in std_logic;		--ureg (jump addr in mem or in address)
--		dmem_write_en : in std_logic;	--ureg
--		hword_hl : in std_logic		--ureg
--	end record;



shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword_hl, wb_reg, result)

begin
	wb_reg_nxt.address <= address;
	wb_reg_nxt.dmem_en <= dmem_en;
	wb_reg_nxt.dmem_write_en <= dmem_write_en;
	wb_reg_nxt.hword <= hword;
	wb_reg_nxt.byte_s <= byte_s;

	regfile_val <= result; --(others => '0');

	if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then	-- ram read operation --alu_jmp = '0' and 
		regfile_val <= data_ram_read;
		if (wb_reg.hword = '1') then
			regfile_val <= (others => '0');
			if (wb_reg.address(1) = '1') then
				regfile_val(15 downto 0) <= data_ram_read(31 downto 16);
			else
				regfile_val(15 downto 0) <= data_ram_read(15 downto 0);
			end if;
		end if;
		if (wb_reg.byte_s = '1') then
			regfile_val <= (others => '0');
			case wb_reg.address(1 downto 0) is
				when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0);
				when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
				when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
				when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
			end case;
		end if;	
	end if;

	jump <= alu_jmp xor br_pred;
	jump_addr <= result;
	if ((alu_jmp and wb_reg.dmem_en) = '1') then
		jump_addr <= data_ram_read;
	end if;

end process;

--			result : in gp_register_t;	--reg  (alu result or jumpaddr)
--			result_addr : in gp_addr_t;	--reg
--			address : in word_t;		--ureg 
--			alu_jmp : in std_logic;		--reg
--			br_pred : in std_logic;		--reg
--			write_en : in std_logic;	--reg  (register file)
--			dmem_en : in std_logic;		--ureg (jump addr in mem or in result)
--			dmem_write_en : in std_logic;	--ureg
--			hword : in std_logic		--ureg



out_logic: process(write_en, result_addr)

begin
	reg_we <= write_en;
	reg_addr <= result_addr;
end process;

end behav;