2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_misc.all;
4 use ieee.std_logic_arith.all;
5 use ieee.std_logic_unsigned.all;
7 use UNISIM.vcomponents.all;
10 generic ( ADDR_WIDTH : integer range 1 to integer'high);
11 port(clk : in std_logic;
12 addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
13 be : in std_logic_vector(3 downto 0);
14 we : in std_logic; -- dummy :/
15 wdata : in std_logic_vector(31 downto 0);
16 q : out std_logic_vector(31 downto 0)