cpu/src/r_w_ram_b.vhd

   1 library ieee;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7
   8 architecture behaviour of r_w_ram is
   9
  10         subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
  11         type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
  12
  13         signal ram : RAM_TYPE := (--0 => "11100000000000011001000000000000",  -- r0 = r3 + r2 (always)
  14                                 --  1 => "11100101000000001000100000000000",  -- r0 = r1 << 0 (always)
  15                                 --  2 => "11100000000010000001100000000000",  -- r1 = r0 + r3 (always)
  16                                 --  3 => "11100000101000000001000000000000",
  17                                 --  4 => "11100001000110010111011001101100",
  18                                   0 => "11101100000000001000000000000000", -- cmp r0 , r1
  19                                   1 => "00000000000100000000100000000000",
  20                                   2 => "00000000001110000001000000000000",
  21                                   3 => "11100001000110010000011001101100",
  22                                   others => x"F0000000");
  23
  24 begin
  25         process(clk)
  26         begin
  27                 if rising_edge(clk) then
  28                         data_out <= ram(to_integer(UNSIGNED(rd_addr)));
  29
  30                         if wr_en = '1' then
  31                                 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
  32                         end if;
  33                 end if;
  34         end process;
  35 end architecture behaviour;