cpu/src/pipeline_tb.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7 use work.extension_pkg.all;
   8 -------------------------------------------------------------------------------
   9 -- ENTITY
  10 -------------------------------------------------------------------------------
  11 entity pipeline_tb is
  12
  13 end pipeline_tb;
  14
  15
  16 -------------------------------------------------------------------------------
  17 -- ARCHITECTURE
  18 -------------------------------------------------------------------------------
  19 architecture behavior of pipeline_tb is
  20
  21         constant cc : time := 30 ns;        -- test clock period
  22
  23                 signal sys_clk_pin : std_logic;
  24                 signal sys_res_n_pin : std_logic;
  25                 --Data input
  26
  27                 signal dummy : std_logic;
  28
  29                 signal jump_result_pin : instruction_addr_t;
  30                 signal prediction_result_pin : instruction_addr_t;
  31                 signal branch_prediction_bit_pin : std_logic;
  32                 signal alu_jump_bit_pin : std_logic;
  33                 signal instruction_pin : instruction_word_t;
  34                 signal prog_cnt : instruction_addr_t;
  35
  36                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  37                 signal reg_wr_data_pin : gp_register_t;
  38                 signal reg_we_pin : std_logic;
  39                 signal to_next_stage_pin : dec_op;
  40
  41                  signal result_pin : gp_register_t;--reg
  42                  signal result_addr_pin : gp_addr_t;--reg
  43                  signal addr_pin : word_t; --memaddr
  44                  signal data_pin : gp_register_t; --mem data --ureg
  45                  signal alu_jump_pin : std_logic;--reg
  46                  signal brpr_pin  : std_logic;  --reg
  47                  signal wr_en_pin : std_logic;--regop --reg
  48                  signal dmem_pin  : std_logic;--memop
  49                  signal dmem_wr_en_pin : std_logic;
  50                  signal hword_pin  : std_logic;
  51                  signal byte_s_pin : std_logic;
  52
  53                                   signal gpm_in_pin : extmod_rec;
  54                                  signal gpm_out_pin : gp_register_t;
  55                  signal nop_pin : std_logic;
  56
  57
  58 begin
  59
  60 --              instruction_ram : r_w_ram
  61 --              generic map (
  62 --                      PHYS_INSTR_ADDR_WIDTH,
  63 --                      WORD_WIDTH
  64 --              )
  65 --
  66 --              port map (
  67 --                      sys_clk,
  68 --                      instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  69 --                      instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  70 --                      instr_we,
  71 --                      instr_wr_data,
  72 --                      instr_rd_data
  73 --              );
  74
  75         fetch_st : fetch_stage
  76                 generic map (
  77
  78                         '0',
  79                         '1'
  80                 )
  81
  82                 port map (
  83                 --System inputs
  84                         clk => sys_clk_pin, --: in std_logic;
  85                         reset => sys_res_n_pin, --: in std_logic;
  86
  87                 --Data inputs
  88                         jump_result => jump_result_pin, --: in instruction_addr_t;
  89                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  90                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  91                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  92
  93                 --Data outputs
  94                         instruction => instruction_pin, --: out instruction_word_t
  95                         prog_cnt => prog_cnt
  96                 );
  97
  98         decode_st : decode_stage
  99                 generic map (
 100                         -- active reset value
 101                         '0',
 102                         -- active logic value
 103                         '1'
 104
 105                         )
 106                 port map (
 107                 --System inputs
 108                         clk => sys_clk_pin, --: in std_logic;
 109                         reset => sys_res_n_pin, -- : in std_logic;
 110
 111                 --Data inputs
 112                         instruction => instruction_pin, --: in instruction_word_t;
 113                         prog_cnt => prog_cnt,
 114                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 115                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
 116                         reg_we => reg_we_pin, --: in std_logic;
 117                         nop => nop_pin,
 118
 119                 --Data outputs
 120                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 121                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 122                         to_next_stage => to_next_stage_pin
 123
 124                 );
 125           exec_st : execute_stage
 126                 generic map('0')
 127                 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
 128                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 129
 130           writeback_st : writeback_stage
 131                 generic map('0', '1')
 132                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 133                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 134                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
 135
 136
 137
 138
 139         nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin);
 140
 141 -------------------------------------------------------------------------------
 142 -- generate simulation clock
 143 -------------------------------------------------------------------------------
 144   CLKGEN : process
 145   begin
 146     sys_clk_pin <= '1';
 147     wait for cc/2;
 148     sys_clk_pin <= '0';
 149     wait for cc/2;
 150   end process CLKGEN;
 151
 152 -------------------------------------------------------------------------------
 153 -- test the design
 154 -------------------------------------------------------------------------------
 155   TEST_IT : process
 156
 157     -- wait for n clock cycles
 158     procedure icwait(cycles : natural) is
 159     begin
 160       for i in 1 to cycles loop
 161         wait until sys_clk_pin = '1' and sys_clk_pin'event;
 162       end loop;
 163     end;
 164
 165   begin
 166     -----------------------------------------------------------------------------
 167     -- initial reset
 168     -----------------------------------------------------------------------------
 169         sys_res_n_pin <= '0';
 170 --      reg_w_addr_pin <= (others => '0');
 171 --      reg_wr_data_pin <= (others => '0');
 172 --      reg_we_pin <= '0';
 173
 174         icwait(10);
 175         dummy <= '1';
 176         sys_res_n_pin <= '1';
 177         wait until sys_res_n_pin = '1';
 178
 179
 180         icwait(100000);
 181
 182     ---------------------------------------------------------------------------
 183     -- exit testbench
 184     ---------------------------------------------------------------------------
 185     assert false
 186       report "Test finished"
 187       severity error;
 188
 189   end process test_it;
 190
 191 end behavior;
 192
 193
 194 -------------------------------------------------------------------------------
 195 -- configuration
 196 -------------------------------------------------------------------------------
 197 configuration pipeline_conf_beh of pipeline_tb is
 198   for behavior
 199     for fetch_st : fetch_stage use entity work.fetch_stage(behav);
 200     end for;
 201     for decode_st : decode_stage use entity work.decode_stage(behav);
 202     end for;
 203     for exec_st : execute_stage use entity work.execute_stage(behav);
 204     end for;
 205     for writeback_st : writeback_stage use entity work.writeback_stage(behav);
 206     end for;
 207
 208   end for;
 209 end pipeline_conf_beh;