2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
8 -------------------------------------------------------------------------------
10 -------------------------------------------------------------------------------
16 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 architecture behavior of pipeline_tb is
21 constant cc : time := 20 ns; -- test clock period
22 constant SYS_CLOCK_FREQ : integer := 50000000;
23 constant BAUD_COUNT : integer := SYS_CLOCK_FREQ/115200;
25 signal sys_clk_pin : std_logic;
26 signal sys_res_n_pin : std_logic;
29 signal dummy : std_logic;
31 signal jump_result_pin : instruction_addr_t;
32 signal prediction_result_pin : instruction_addr_t;
33 signal branch_prediction_bit_pin : std_logic;
34 signal alu_jump_bit_pin : std_logic;
35 signal instruction_pin : instruction_word_t;
36 signal prog_cnt : instruction_addr_t;
38 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
39 signal reg_wr_data_pin : gp_register_t;
40 signal reg_we_pin : std_logic;
41 signal to_next_stage_pin : dec_op;
43 signal result_pin : gp_register_t;--reg
44 signal result_addr_pin : gp_addr_t;--reg
45 signal addr_pin : word_t; --memaddr
46 signal data_pin : gp_register_t; --mem data --ureg
47 signal alu_jump_pin : std_logic;--reg
48 signal brpr_pin : std_logic; --reg
49 signal wr_en_pin : std_logic;--regop --reg
50 signal dmem_pin : std_logic;--memop
51 signal dmem_wr_en_pin : std_logic;
52 signal hword_pin : std_logic;
53 signal byte_s_pin, tx_pin, rx_pin : std_logic;
55 signal gpm_in_pin : extmod_rec;
56 signal gpm_out_pin : gp_register_t;
57 signal nop_pin : std_logic;
59 signal cycle_cnt : integer;
61 signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
62 signal int_req_pin : interrupt_t;
64 signal new_im_data :std_logic;
65 signal im_addr, im_data : gp_register_t;
69 -- instruction_ram : r_w_ram
71 -- PHYS_INSTR_ADDR_WIDTH,
77 -- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
78 -- instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
84 fetch_st : fetch_stage
93 clk => sys_clk_pin, --: in std_logic;
94 reset => sys_res_n_pin, --: in std_logic;
97 jump_result => jump_result_pin, --: in instruction_addr_t;
98 prediction_result => prediction_result_pin, --: in instruction_addr_t;
99 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
100 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
101 new_im_data_in => new_im_data,
106 instruction => instruction_pin, --: out instruction_word_t
107 prog_cnt => prog_cnt,
108 int_req => int_req_pin
111 decode_st : decode_stage
113 -- active reset value
115 -- active logic value
121 clk => sys_clk_pin, --: in std_logic;
122 reset => sys_res_n_pin, -- : in std_logic;
125 instruction => instruction_pin, --: in instruction_word_t;
126 prog_cnt => prog_cnt,
127 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
128 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
129 reg_we => reg_we_pin, --: in std_logic;
133 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
134 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
135 to_next_stage => to_next_stage_pin
138 exec_st : execute_stage
140 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
141 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
143 writeback_st : writeback_stage
144 generic map('0', '1', "altera",50)
145 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
146 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
147 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);
152 nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin);
154 -------------------------------------------------------------------------------
155 -- generate simulation clock
156 -------------------------------------------------------------------------------
166 cnt : process(sys_clk_pin, sys_res_n_pin)
170 if (sys_res_n_pin = '0') then
172 elsif (sys_clk_pin'event and sys_clk_pin = '1') then
173 cycle_cnt <= cycle_cnt + 1;
177 -------------------------------------------------------------------------------
179 -------------------------------------------------------------------------------
182 -- wait for n clock cycles
183 procedure icwait(cycles : natural) is
185 for i in 1 to cycles loop
186 wait until sys_clk_pin = '1' and sys_clk_pin'event;
190 procedure txd(trans_data : in std_logic_vector) is
193 rx_pin <= trans_data(i);
194 report "bit: " & std_logic'image(trans_data(i));
197 -- icwait(BAUD_COUNT);
204 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207 sys_res_n_pin <= '0';
209 -- reg_w_addr_pin <= (others => '0');
210 -- reg_wr_data_pin <= (others => '0');
211 -- reg_we_pin <= '0';
215 sys_res_n_pin <= '1';
216 wait until sys_res_n_pin = '1';
227 ---------------------------------------------------------------------------
229 ---------------------------------------------------------------------------
231 report "Test finished"
239 -------------------------------------------------------------------------------
241 -------------------------------------------------------------------------------
242 configuration pipeline_conf_beh of pipeline_tb is
244 for fetch_st : fetch_stage use entity work.fetch_stage(behav);
246 for decode_st : decode_stage use entity work.decode_stage(behav);
248 for exec_st : execute_stage use entity work.execute_stage(behav);
250 for writeback_st : writeback_stage use entity work.writeback_stage(behav);
254 end pipeline_conf_beh;