added soft reset

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 6815be1dbffc6d808f0839d9c8a500f0fafcb282..f3e132328db24cfdc16516be3954a6a24673f47a 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -11,6 +11,7 @@ entity core_top is
        port(
                --System input pins
                   sys_res : in std_logic;
+                       soft_res : in std_logic;
                        sys_clk : in std_logic;
 --                     result : out gp_register_t;
 --                     reg_wr_data : out gp_register_t
@@ -64,8 +65,8 @@ architecture behav of core_top is
                 signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
                 
-                signal sync : std_logic_vector(1 to SYNC_STAGES);
-                signal sys_res_n : std_logic;
+                signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES);
+                signal sys_res_n, soft_res_n : std_logic;
 
                 signal int_req : interrupt_t;
 
@@ -86,7 +87,7 @@ begin
                --System inputs
                        clk => sys_clk, --: in std_logic;
                        reset => sys_res_n, --: in std_logic;
-                       s_reset => '1',
+                       s_reset => soft_res_n,
                --Data inputs
                        jump_result => jump_result_pin, --: in instruction_addr_t;
                        prediction_result => prediction_result_pin, --: in instruction_addr_t;
@@ -114,7 +115,7 @@ begin
                port map (
                --System inputs
                        clk => sys_clk, --: in std_logic;
-                       reset => sys_res_n, -- : in std_logic;
+                       reset => sys_res_n and soft_res_n, -- : in std_logic;
 
                --Data inputs
                        instruction => instruction_pin, --: in instruction_word_t;
@@ -132,7 +133,7 @@ begin
 
           exec_st : execute_stage
                 generic map('0')
-                port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+                port map(sys_clk, sys_res_n and soft_res_n, to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
 
@@ -157,7 +158,7 @@ begin
 
                        writeback_st : writeback_stage
                 generic map('0', '1', "altera", 2083)
-                port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
+                port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
                                -- instruction memory program port :D
@@ -165,7 +166,7 @@ begin
                                sseg0, sseg1, sseg2, sseg3, int_req);
 
 
-syn: process(sys_clk, sys_res)
+syn: process(sys_clk, sys_res, soft_res)
 
 begin
 
@@ -183,6 +184,7 @@ begin
 --                     vers.byte_s <= '0';
        
                sync <= (others => '0');
+               sync2 <= (others => '0');
        
        elsif rising_edge(sys_clk) then
 --             vers <= vers_nxt;
@@ -190,12 +192,17 @@ begin
                        for i in 2 to SYNC_STAGES loop
                                sync(i) <= sync(i - 1);
                        end loop;
-                               
+                       sync2(1) <= not soft_res;
+                       for i in 2 to SYNC_STAGES loop
+                               sync2(i) <= sync2(i - 1);
+                       end loop;
        end if;
+
        
 end process;
 
 sys_res_n <= sync(SYNC_STAGES);
+soft_res_n <= sync2(SYNC_STAGES);
        
 --init : process(all)
 

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index f01bad8f68c4b3b9f3fc2b1700f6e56c0c7812d4..c975af29702992b673c6c8fce467f19ba2ceeb20 100644 (file)
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -68,10 +68,10 @@ variable instr_pc  : instruction_addr_t;
 begin
        rom_ram_nxt <= rom_ram;
        
-       if (s_reset = RESET_VALUE) then
-               rom_ram_nxt <= RAM_USE;
-               instr_r_addr_nxt <= (others => '0');
-       end if;
+--     if (s_reset = RESET_VALUE) then
+--             rom_ram_nxt <= RAM_USE;
+--             instr_r_addr_nxt <= (others => '0');
+--     end if;
        
        case rom_ram is
                when ROM_USE =>

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index 47406cab3f02f6b55dbf13bee70f23c3c9ab26a3..eda81023058f86351b0850bded6ddccc83fd102a 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -92,7 +92,7 @@ begin
                --System inputs
                        clk => sys_clk_pin, --: in std_logic;
                        reset => sys_res_n_pin, --: in std_logic;
-               
+                       s_reset => '0',
                --Data inputs
                        jump_result => jump_result_pin, --: in instruction_addr_t;
                        prediction_result => prediction_result_pin, --: in instruction_addr_t;
@@ -141,7 +141,7 @@ begin
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
           writeback_st : writeback_stage
-                generic map('0', '1', "altera")
+                generic map('0', '1', "altera",50)
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);

diff --git a/dt/dt.qsf b/dt/dt.qsf
index aed8015bc2cf17e1f63ababa3ec2a1953161a4cd..8180379336117b0e8aa89b6619640e10d772c6cb 100644 (file)
--- a/dt/dt.qsf
+++ b/dt/dt.qsf
@@ -78,6 +78,11 @@ set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
 set_global_assignment -name MUX_RESTRUCTURE OFF
 set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
 set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
+
+
+
+
+set_global_assignment -name VHDL_FILE ../cpu/src/core_top_c2de1.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd
@@ -131,8 +136,6 @@ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
-
-
-
-
+set_location_assignment PIN_41 -to soft_res
+set_global_assignment -name MISC_FILE /homes/c0725782/calu/dt/dt.dpf
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file