cpu/src/pipeline_tb.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7 use work.extension_pkg.all;
   8 -------------------------------------------------------------------------------
   9 -- ENTITY
  10 -------------------------------------------------------------------------------
  11 entity pipeline_tb is
  12
  13 end pipeline_tb;
  14
  15
  16 -------------------------------------------------------------------------------
  17 -- ARCHITECTURE
  18 -------------------------------------------------------------------------------
  19 architecture behavior of pipeline_tb is
  20
  21         constant cc : time := 30 ns;        -- test clock period
  22
  23                 signal sys_clk_pin : std_logic;
  24                 signal sys_res_n_pin : std_logic;
  25                 --Data input
  26
  27                 signal dummy : std_logic;
  28
  29                 signal jump_result_pin : instruction_addr_t;
  30                 signal prediction_result_pin : instruction_addr_t;
  31                 signal branch_prediction_bit_pin : std_logic;
  32                 signal alu_jump_bit_pin : std_logic;
  33                 signal instruction_pin : instruction_word_t;
  34
  35                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  36                 signal reg_wr_data_pin : gp_register_t;
  37                 signal reg_we_pin : std_logic;
  38                 signal to_next_stage_pin : dec_op;
  39
  40                  signal result_pin : gp_register_t;--reg
  41                  signal result_addr_pin : gp_addr_t;--reg
  42                  signal addr_pin : word_t; --memaddr
  43                  signal data_pin : gp_register_t; --mem data --ureg
  44                  signal alu_jump_pin : std_logic;--reg
  45                  signal brpr_pin  : std_logic;  --reg
  46                  signal wr_en_pin : std_logic;--regop --reg
  47                  signal dmem_pin  : std_logic;--memop
  48                  signal dmem_wr_en_pin : std_logic;
  49                  signal hword_pin  : std_logic;
  50                  signal byte_s_pin : std_logic;
  51                  signal nop_pin : std_logic;
  52
  53
  54 begin
  55
  56 --              instruction_ram : r_w_ram
  57 --              generic map (
  58 --                      PHYS_INSTR_ADDR_WIDTH,
  59 --                      WORD_WIDTH
  60 --              )
  61 --
  62 --              port map (
  63 --                      sys_clk,
  64 --                      instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  65 --                      instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  66 --                      instr_we,
  67 --                      instr_wr_data,
  68 --                      instr_rd_data
  69 --              );
  70
  71         fetch_st : fetch_stage
  72                 generic map (
  73
  74                         '0',
  75                         '1'
  76                 )
  77
  78                 port map (
  79                 --System inputs
  80                         clk => sys_clk_pin, --: in std_logic;
  81                         reset => sys_res_n_pin, --: in std_logic;
  82
  83                 --Data inputs
  84                         jump_result => jump_result_pin, --: in instruction_addr_t;
  85                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  86                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  87                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  88
  89                 --Data outputs
  90                         instruction => instruction_pin --: out instruction_word_t
  91                 );
  92
  93         decode_st : decode_stage
  94                 generic map (
  95                         -- active reset value
  96                         '0',
  97                         -- active logic value
  98                         '1'
  99
 100                         )
 101                 port map (
 102                 --System inputs
 103                         clk => sys_clk_pin, --: in std_logic;
 104                         reset => sys_res_n_pin, -- : in std_logic;
 105
 106                 --Data inputs
 107                         instruction => instruction_pin, --: in instruction_word_t;
 108                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 109                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
 110                         reg_we => reg_we_pin, --: in std_logic;
 111                         nop => nop_pin,
 112
 113                 --Data outputs
 114                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 115                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 116                         to_next_stage => to_next_stage_pin
 117
 118                 );
 119           exec_st : execute_stage
 120                 generic map('0')
 121                 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
 122                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
 123
 124           writeback_st : writeback_stage
 125                 generic map('0', '1')
 126                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 127                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 128                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
 129
 130
 131
 132
 133         nop_pin <= (alu_jump_bit_pin xor brpr_pin);
 134
 135 -------------------------------------------------------------------------------
 136 -- generate simulation clock
 137 -------------------------------------------------------------------------------
 138   CLKGEN : process
 139   begin
 140     sys_clk_pin <= '1';
 141     wait for cc/2;
 142     sys_clk_pin <= '0';
 143     wait for cc/2;
 144   end process CLKGEN;
 145
 146 -------------------------------------------------------------------------------
 147 -- test the design
 148 -------------------------------------------------------------------------------
 149   TEST_IT : process
 150
 151     -- wait for n clock cycles
 152     procedure icwait(cycles : natural) is
 153     begin
 154       for i in 1 to cycles loop
 155         wait until sys_clk_pin = '1' and sys_clk_pin'event;
 156       end loop;
 157     end;
 158
 159   begin
 160     -----------------------------------------------------------------------------
 161     -- initial reset
 162     -----------------------------------------------------------------------------
 163         sys_res_n_pin <= '0';
 164 --      reg_w_addr_pin <= (others => '0');
 165 --      reg_wr_data_pin <= (others => '0');
 166 --      reg_we_pin <= '0';
 167
 168         icwait(10);
 169         dummy <= '1';
 170         sys_res_n_pin <= '1';
 171         wait until sys_res_n_pin = '1';
 172
 173
 174         icwait(100000);
 175
 176     ---------------------------------------------------------------------------
 177     -- exit testbench
 178     ---------------------------------------------------------------------------
 179     assert false
 180       report "Test finished"
 181       severity error;
 182
 183   end process test_it;
 184
 185 end behavior;
 186
 187
 188 -------------------------------------------------------------------------------
 189 -- configuration
 190 -------------------------------------------------------------------------------
 191 configuration pipeline_conf_beh of pipeline_tb is
 192   for behavior
 193     for fetch_st : fetch_stage use entity work.fetch_stage(behav);
 194     end for;
 195     for decode_st : decode_stage use entity work.decode_stage(behav);
 196     end for;
 197     for exec_st : execute_stage use entity work.execute_stage(behav);
 198     end for;
 199     for writeback_st : writeback_stage use entity work.writeback_stage(behav);
 200     end for;
 201
 202   end for;
 203 end pipeline_conf_beh;