cpu/src/pipeline_tb.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7 use work.extension_pkg.all;
   8 -------------------------------------------------------------------------------
   9 -- ENTITY
  10 -------------------------------------------------------------------------------
  11 entity pipeline_tb is
  12
  13 end pipeline_tb;
  14
  15
  16 -------------------------------------------------------------------------------
  17 -- ARCHITECTURE
  18 -------------------------------------------------------------------------------
  19 architecture behavior of pipeline_tb is
  20
  21         constant cc : time := 30 ns;        -- test clock period
  22
  23                 signal sys_clk_pin : std_logic;
  24                 signal sys_res_n_pin : std_logic;
  25                 --Data input
  26
  27                 signal dummy : std_logic;
  28
  29                 signal jump_result_pin : instruction_addr_t;
  30                 signal prediction_result_pin : instruction_addr_t;
  31                 signal branch_prediction_bit_pin : std_logic;
  32                 signal alu_jump_bit_pin : std_logic;
  33                 signal instruction_pin : instruction_word_t;
  34
  35                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  36                 signal reg_wr_data_pin : gp_register_t;
  37                 signal reg_we_pin : std_logic;
  38                 signal to_next_stage_pin : dec_op;
  39
  40                  signal result_pin : gp_register_t;--reg
  41                  signal result_addr_pin : gp_addr_t;--reg
  42                  signal addr_pin : word_t; --memaddr
  43                  signal data_pin : gp_register_t; --mem data --ureg
  44                  signal alu_jump_pin : std_logic;--reg
  45                  signal brpr_pin  : std_logic;  --reg
  46                  signal wr_en_pin : std_logic;--regop --reg
  47                  signal dmem_pin  : std_logic;--memop
  48                  signal dmem_wr_en_pin : std_logic;
  49                  signal hword_pin  : std_logic;
  50                  signal byte_s_pin : std_logic;
  51                  signal nop_pin : std_logic;
  52                 -- extension signals
  53                 signal ext_gpmp :  extmod_rec;
  54                 signal pointer : pointer_count;
  55                 signal dec_in,p_en : std_logic;
  56                 signal data_out    : gp_register_t;
  57                 signal pointer_val : gp_register_t;
  58
  59 begin
  60
  61 --              instruction_ram : r_w_ram
  62 --              generic map (
  63 --                      PHYS_INSTR_ADDR_WIDTH,
  64 --                      WORD_WIDTH
  65 --              )
  66 --
  67 --              port map (
  68 --                      sys_clk,
  69 --                      instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  70 --                      instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  71 --                      instr_we,
  72 --                      instr_wr_data,
  73 --                      instr_rd_data
  74 --              );
  75
  76         fetch_st : fetch_stage
  77                 generic map (
  78
  79                         '0',
  80                         '1'
  81                 )
  82
  83                 port map (
  84                 --System inputs
  85                         clk => sys_clk_pin, --: in std_logic;
  86                         reset => sys_res_n_pin, --: in std_logic;
  87
  88                 --Data inputs
  89                         jump_result => jump_result_pin, --: in instruction_addr_t;
  90                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  91                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  92                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  93
  94                 --Data outputs
  95                         instruction => instruction_pin --: out instruction_word_t
  96                 );
  97
  98         decode_st : decode_stage
  99                 generic map (
 100                         -- active reset value
 101                         '0',
 102                         -- active logic value
 103                         '1'
 104
 105                         )
 106                 port map (
 107                 --System inputs
 108                         clk => sys_clk_pin, --: in std_logic;
 109                         reset => sys_res_n_pin, -- : in std_logic;
 110
 111                 --Data inputs
 112                         instruction => instruction_pin, --: in instruction_word_t;
 113                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 114                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
 115                         reg_we => reg_we_pin, --: in std_logic;
 116                         nop => nop_pin,
 117
 118                 --Data outputs
 119                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 120                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 121                         to_next_stage => to_next_stage_pin
 122
 123                 );
 124           exec_st : execute_stage
 125                 generic map('0')
 126                 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
 127                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
 128
 129           writeback_st : writeback_stage
 130                 generic map('0', '1')
 131                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 132                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 133                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
 134
 135
 136         gpmp_inst :  extension
 137                 generic map ('0')
 138                 port map (
 139                         sys_clk_pin,
 140                         sys_res_n_pin,
 141                         ext_gpmp,
 142                         pointer,
 143                         dec_in,
 144                         p_en,
 145                         data_out,
 146                         pointer_val
 147
 148                 );
 149
 150
 151
 152         nop_pin <= (alu_jump_bit_pin xor brpr_pin);
 153
 154 -------------------------------------------------------------------------------
 155 -- generate simulation clock
 156 -------------------------------------------------------------------------------
 157   CLKGEN : process
 158   begin
 159     sys_clk_pin <= '1';
 160     wait for cc/2;
 161     sys_clk_pin <= '0';
 162     wait for cc/2;
 163   end process CLKGEN;
 164
 165 -------------------------------------------------------------------------------
 166 -- test the design
 167 -------------------------------------------------------------------------------
 168   TEST_IT : process
 169
 170     -- wait for n clock cycles
 171     procedure icwait(cycles : natural) is
 172     begin
 173       for i in 1 to cycles loop
 174         wait until sys_clk_pin = '1' and sys_clk_pin'event;
 175       end loop;
 176     end;
 177
 178   begin
 179     -----------------------------------------------------------------------------
 180     -- initial reset
 181     -----------------------------------------------------------------------------
 182         sys_res_n_pin <= '0';
 183 --      reg_w_addr_pin <= (others => '0');
 184 --      reg_wr_data_pin <= (others => '0');
 185 --      reg_we_pin <= '0';
 186
 187         icwait(10);
 188         dummy <= '1';
 189         sys_res_n_pin <= '1';
 190         wait until sys_res_n_pin = '1';
 191
 192
 193         icwait(100000);
 194
 195     ---------------------------------------------------------------------------
 196     -- exit testbench
 197     ---------------------------------------------------------------------------
 198     assert false
 199       report "Test finished"
 200       severity error;
 201
 202   end process test_it;
 203
 204 end behavior;
 205
 206
 207 -------------------------------------------------------------------------------
 208 -- configuration
 209 -------------------------------------------------------------------------------
 210 configuration pipeline_conf_beh of pipeline_tb is
 211   for behavior
 212     for fetch_st : fetch_stage use entity work.fetch_stage(behav);
 213     end for;
 214     for decode_st : decode_stage use entity work.decode_stage(behav);
 215     end for;
 216     for exec_st : execute_stage use entity work.execute_stage(behav);
 217     end for;
 218     for writeback_st : writeback_stage use entity work.writeback_stage(behav);
 219     end for;
 220
 221   end for;
 222 end pipeline_conf_beh;