library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.core_pkg.all;
use work.common_pkg.all;
use work.mem_pkg.all;

architecture behav of fetch_stage is

signal instr_w_addr 	 : instruction_addr_t;
signal instr_r_addr  	 : instruction_addr_t;
signal instr_r_addr_nxt  : instruction_addr_t;
signal instr_we      	 : std_logic;
signal instr_wr_data 	 : instruction_word_t;
signal instr_rd_data_rom, instr_rd_data 	 : instruction_word_t;
signal rom_ram, rom_ram_nxt : std_logic;

begin

	instruction_ram : r_w_ram --rom
		generic map (
			PHYS_INSTR_ADDR_WIDTH,
			WORD_WIDTH
		)
		
		port map (
			clk,
			im_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
			instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
			new_im_data_in,
			im_data,
			instr_rd_data
		);
		
	instruction_rom : rom
		generic map (
			ROM_INSTR_ADDR_WIDTH,
			WORD_WIDTH
		)
		
		port map (
			clk,
			instr_r_addr_nxt(ROM_INSTR_ADDR_WIDTH-1 downto 0),
			instr_rd_data_rom
		);
		

syn: process(clk, reset)

begin

	if (reset = RESET_VALUE) then
		instr_r_addr <= (others => '0');
		rom_ram <= ROM_USE;
		led2 <= '0';
	elsif rising_edge(clk) then
		instr_r_addr <= instr_r_addr_nxt;		
		rom_ram <= rom_ram_nxt;
		led2 <= rom_ram; --rom_ram_nxt;
	end if;
	
end process; 


asyn: process(reset, s_reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
variable instr_pc  : instruction_addr_t;
begin
	rom_ram_nxt <= rom_ram;
	
	case rom_ram is
		when ROM_USE =>
			instruction <= instr_rd_data_rom;
		when RAM_USE =>
			instruction <= instr_rd_data;
		when others => 
			instruction <= x"F0000000";
	end case;
	instr_pc := std_logic_vector(unsigned(instr_r_addr) + 1);
	instr_r_addr_nxt <= instr_pc;

	if (instr_pc = x"0000007f" and rom_ram = ROM_USE) then
		rom_ram_nxt <= RAM_USE;
		instr_r_addr_nxt <= (others => '0');
	end if;

	if (reset = RESET_VALUE) then
		instr_r_addr_nxt <= (others => '0');
	end if;

	if (alu_jump_bit = LOGIC_ACT and int_req = IDLE) then
		instr_r_addr_nxt <= jump_result;
		instruction(31 downto 28) <= "1111";	
	elsif (branch_prediction_bit = LOGIC_ACT) then
		instr_r_addr_nxt <= prediction_result;
	end if;	

	case int_req is
		when UART =>
			instruction(31 downto 0) <= (others => '0');
			instruction(31 downto 28) <= "1110";
			instruction(27 downto 23) <= "10110";
			instruction(PHYS_INSTR_ADDR_WIDTH + 7 - 1 downto 7) <= UART_INT_VECTOR;
			instruction(6 downto 4) <= "001";
			instruction(3 downto 2) <= "01";
			instruction(1 downto 0) <= "10";

--			instr_r_addr_nxt <= instr_r_addr; 
		when others => null;
	end case;

	if (s_reset = RESET_VALUE) then
		rom_ram_nxt <= RAM_USE;
		instr_r_addr_nxt <= (others => '0');
	end if;	

end process;

out_logic : process (instr_r_addr, alu_jump_bit, int_req, jump_result)

begin
	prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
	prog_cnt(INSTR_ADDR_WIDTH-1 downto PHYS_INSTR_ADDR_WIDTH) <= (others => '0');

	if (int_req /= IDLE and alu_jump_bit = LOGIC_ACT ) then
		prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= jump_result(PHYS_INSTR_ADDR_WIDTH-1 downto 0);
	end if;

end process;

end behav;