cpu/src/extension_uart_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 use work.mem_pkg.all;
   9 use work.extension_pkg.all;
  10 use work.extension_uart_pkg.all;
  11
  12 architecture behav of extension_uart is
  13
  14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
  15 signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
  16 signal  bd_rate : baud_rate_l;
  17 signal rx_data : std_logic_vector(7 downto 0);
  18 begin
  19
  20
  21 rs232_tx_inst : rs232_tx
  22 generic map(
  23                 RESET_VALUE
  24                 )
  25 port map(
  26         --System inputs
  27         clk,
  28         reset,
  29
  30         --Bus
  31         bus_tx,
  32
  33         --From/to sendlogic
  34         new_tx_data,
  35         w3_uart_send(byte_t'range),
  36         tx_rdy,
  37         bd_rate,
  38         w1_st_co(0)
  39 );
  40
  41 rs232_rx_inst : rs232_rx
  42 generic map(
  43                 RESET_VALUE,
  44                 2
  45                 )
  46 port map(
  47         --System inputs
  48         clk,
  49         reset,
  50
  51         --Bus
  52         bus_rx,
  53
  54         --From/to sendlogic
  55         new_bus_rx,
  56         rx_data,
  57         bd_rate
  58 );
  59
  60
  61
  62
  63 syn : process (clk, reset)
  64 begin
  65         if (reset = RESET_VALUE) then
  66                 w1_st_co <= (others=>'0');
  67                 w2_uart_config(31 downto 16) <= (others=>'0');
  68                 -- todo mit einer konstante versehen
  69                 w2_uart_config(15 downto 0) <= x"01B2";
  70                 w3_uart_send <= (others=>'0');
  71                 w4_uart_receive <= (others=>'0');
  72                 tx_rdy_int <= '0';
  73                 new_tx_data <= '0';
  74
  75         elsif rising_edge(clk) then
  76                 w1_st_co <= w1_st_co_nxt;
  77                 w2_uart_config <= w2_uart_config_nxt;
  78                 w3_uart_send <= w3_uart_send_nxt;
  79                 w4_uart_receive <= w4_uart_receive_nxt;
  80                 new_tx_data <= new_tx_data_nxt;
  81                 tx_rdy_int <= tx_rdy;
  82         end if;
  83 end process syn;
  84
  85 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
  86
  87 gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx)
  88
  89 variable tmp_data  : gp_register_t;
  90
  91 begin
  92
  93                 w1_st_co_nxt <= w1_st_co;
  94                 w2_uart_config_nxt <= w2_uart_config;
  95                 w3_uart_send_nxt <= w3_uart_send;
  96                 w4_uart_receive_nxt <= w4_uart_receive;
  97
  98         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
  99                 tmp_data := (others =>'0');
 100                 if ext_reg.byte_en(0) = '1' then
 101                         tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
 102                 end if;
 103                 if ext_reg.byte_en(1) = '1' then
 104                         tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
 105                 end if;
 106                 if ext_reg.byte_en(2) = '1' then
 107                         tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
 108                 end if;
 109                 if ext_reg.byte_en(3) = '1' then
 110                         tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
 111                 end if;
 112
 113                 case ext_reg.addr(1 downto 0) is
 114                 when "00" =>
 115                         w1_st_co_nxt <= tmp_data;
 116                 when "01" =>
 117                         w2_uart_config_nxt <= tmp_data;
 118                 when "10" =>
 119                         w1_st_co_nxt(16) <= '1'; -- busy flag set
 120                         w3_uart_send_nxt <= tmp_data;
 121                 when "11" =>
 122                         --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
 123                 when others => null;
 124                 end case;
 125         end if;
 126
 127         if  tx_rdy = '1' and tx_rdy_int = '0' then
 128                 w1_st_co_nxt(16) <= '0'; -- busy flag reset
 129         end if;
 130
 131         if new_bus_rx = '1' then
 132                 w4_uart_receive_nxt(7 downto 0) <= rx_data;
 133                 w1_st_co_nxt(17) <= '1';
 134         end if;
 135
 136
 137 end process gwriten;
 138
 139 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
 140
 141 variable tmp_data  : gp_register_t;
 142
 143 begin
 144         if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
 145                 case ext_reg.addr(1 downto 0) is
 146                 when "00" =>
 147                         tmp_data := (others =>'0');
 148                         if ext_reg.byte_en(0) = '1' then
 149                                 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
 150                         end if;
 151                         if ext_reg.byte_en(1) = '1' then
 152                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
 153                         end if;
 154                         if ext_reg.byte_en(2) = '1' then
 155                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
 156                         end if;
 157                         if ext_reg.byte_en(3) = '1' then
 158                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
 159                         end if;
 160                         data_out <= tmp_data;
 161                 when "01" =>
 162                         tmp_data := (others =>'0');
 163                         if ext_reg.byte_en(0) = '1' then
 164                                 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
 165                         end if;
 166                         if ext_reg.byte_en(1) = '1' then
 167                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
 168                         end if;
 169                         if ext_reg.byte_en(2) = '1' then
 170                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
 171                         end if;
 172                         if ext_reg.byte_en(3) = '1' then
 173                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
 174                         end if;
 175                         data_out <= tmp_data;
 176                 when "10" =>
 177                         tmp_data := (others =>'0');
 178                         if ext_reg.byte_en(0) = '1' then
 179                                 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
 180                         end if;
 181                         if ext_reg.byte_en(1) = '1' then
 182                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
 183                         end if;
 184                         if ext_reg.byte_en(2) = '1' then
 185                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
 186                         end if;
 187                         if ext_reg.byte_en(3) = '1' then
 188                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
 189                         end if;
 190                         data_out <= tmp_data;
 191                 when "11" =>
 192                         tmp_data := (others =>'0');
 193                         if ext_reg.byte_en(0) = '1' then
 194                                 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
 195                         end if;
 196                         if ext_reg.byte_en(1) = '1' then
 197                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
 198                         end if;
 199                         if ext_reg.byte_en(2) = '1' then
 200                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
 201                         end if;
 202                         if ext_reg.byte_en(3) = '1' then
 203                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
 204                         end if;
 205                         data_out <= tmp_data;
 206                 when others => null;
 207                 end case;
 208         else
 209                 data_out  <= (others=>'0');
 210         end if;
 211 end process gread;
 212
 213
 214 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
 215
 216 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
 217
 218 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
 219
 220
 221 begin
 222
 223         new_tx_data_nxt <= '0';
 224         bd_rate <= w2_uart_config(15 downto 0);
 225
 226         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 227                 case ext_reg.addr(1 downto 0) is
 228                 when "00" =>
 229
 230                 when "01" =>
 231
 232                 when "10" =>
 233                         new_tx_data_nxt <= '1';
 234                 when "11" =>
 235
 236                 when others => null;
 237                 end case;
 238         end if;
 239
 240 end process dataprocess;
 241
 242
 243
 244 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
 245
 246 end behav;
 247