2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4 use IEEE.STD_LOGIC_ARITH.ALL;
5 use IEEE.STD_LOGIC_UNSIGNED.ALL;
7 use work.common_pkg.all;
12 use work.extension_pkg.all;
13 use work.extension_timer_pkg.all;
15 architecture behav of extension_timer is
17 signal w1_st_co, w1_st_co_nxt, w2_im_val, w2_im_val_nxt : gp_register_t;
18 signal w3_im_notused, w3_im_notused_nxt, w4_im_notused, w4_im_notused_nxt : gp_register_t;
22 syn : process (clk, reset)
24 if (reset = RESET_VALUE) then
25 w1_st_co <= (others => '0');
26 w2_im_val <= (others => '0');
27 w3_im_notused <= (others => '0');
28 w4_im_notused <= (others => '0');
29 elsif rising_edge(clk) then
30 w1_st_co <= w1_st_co_nxt;
31 w2_im_val <= w2_im_val_nxt;
32 w3_im_notused <= w3_im_notused_nxt;
33 w4_im_notused <= w4_im_notused_nxt;
37 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
39 gwriten : process (ext_reg, w1_st_co, w2_im_val, w3_im_notused, w4_im_notused)
40 variable tmp_data : gp_register_t;
42 w1_st_co_nxt <= w1_st_co;
43 w2_im_val_nxt <= w2_im_val;
44 w3_im_notused_nxt <= w3_im_notused;
45 w4_im_notused_nxt <= w4_im_notused;
48 if (w1_st_co(0) = '1') then -- timer enabled?
49 w2_im_val_nxt <= std_logic_vector(IEEE.numeric_std.unsigned(w2_im_val) + 1);
50 -- n00b overflow (logic elements sparen...)
51 if(w2_im_val(31) = '1') then
52 w1_st_co_nxt(16) <= '1';
56 if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
57 tmp_data := (others =>'0');
59 if ext_reg.byte_en(i) = '1' then
60 tmp_data(((i+1)*byte_t'length-1) downto i*byte_t'length) := ext_reg.data(((i+1)*byte_t'length-1) downto i*byte_t'length);
64 case ext_reg.addr(1 downto 0) is
65 when "00" => -- status/config
66 w1_st_co_nxt <= tmp_data;
67 when "01" => -- timer value
68 w2_im_val_nxt <= tmp_data;
76 gread : process (clk, ext_reg, w1_st_co, w2_im_val, w3_im_notused, w4_im_notused)
77 variable tmp_data : gp_register_t;
79 tmp_data := (others => '0');
80 if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
81 case ext_reg.addr(1 downto 0) is
82 when "00" => put_word_be(tmp_data, w1_st_co, ext_reg.byte_en);
83 when "01" => put_word_be(tmp_data, w2_im_val, ext_reg.byte_en);
84 when "10" => put_word_be(tmp_data, w3_im_notused, ext_reg.byte_en);
85 when "11" => put_word_be(tmp_data, w4_im_notused, ext_reg.byte_en);
92 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
93 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
94 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------