1 -- `Deep Thought', a softcore CPU implemented on a FPGA
3 -- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
4 -- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
5 -- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
6 -- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
7 -- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
9 -- This program is free software: you can redistribute it and/or modify
10 -- it under the terms of the GNU General Public License as published by
11 -- the Free Software Foundation, either version 3 of the License, or
12 -- (at your option) any later version.
14 -- This program is distributed in the hope that it will be useful,
15 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
16 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 -- GNU General Public License for more details.
19 -- You should have received a copy of the GNU General Public License
20 -- along with this program. If not, see <http://www.gnu.org/licenses/>.
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
26 use work.common_pkg.all;
27 use work.core_pkg.all;
30 use work.extension_pkg.all;
32 architecture behav of extension_gpm is
34 type pointers_t is array( 0 to ((2**(paddr_t'length))-1)) of ext_addr_t;
36 type gpm_internal is record
39 end record gpm_internal;
41 signal reg, reg_nxt : gpm_internal;
45 syn : process (clk, reset)
47 if (reset = RESET_VALUE) then
48 reg.status <= (others=>'0');
49 reg.preg <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,reg.preg(0)'length))));
50 elsif rising_edge(clk) then
55 asyn : process (clk, reset, reg, psw_nxt, ext_reg, pwr_en, pinc, paddr)
56 variable reg_nxt_v : gpm_internal;
57 variable incb : ext_addr_t;
58 variable sel_pval, sel_pval_nxt : ext_addr_t;
60 variable data_out_v : gp_register_t;
61 variable data_v : gp_register_t;
62 variable tmp_data : gp_register_t;
66 data_v := ext_reg.data;
70 data_out_v := (others => '0');
74 incb(incb'high downto 1) := (others => '1');
76 incb(incb'high downto 1) := (others => '0');
79 sel_pval:= reg_nxt_v.preg(0);
80 sel_pval_nxt := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
82 reg_nxt_v.preg(0) := sel_pval_nxt;
85 reg_nxt_v.status := psw_nxt;
88 data_out <= data_out_v;
90 pval <= (others =>'0');
91 pval(pval'high downto BYTEADDR) <= sel_pval;
92 pval_nxt <= (others =>'0');
93 pval_nxt(pval'high downto BYTEADDR) <= sel_pval_nxt;