--   `Deep Thought', a softcore CPU implemented on a FPGA
--
--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.common_pkg.all;
use work.core_pkg.all;

use work.mem_pkg.all;
use work.extension_pkg.all;

architecture behav of extension_gpm is

type pointers_t is array( 0 to ((2**(paddr_t'length))-1)) of ext_addr_t;

type gpm_internal is record
    status : status_rec;
	preg : pointers_t;
end record gpm_internal;

signal reg, reg_nxt : gpm_internal;


begin
syn : process (clk, reset)
begin
        if (reset = RESET_VALUE) then
                reg.status <= (others=>'0');
		reg.preg <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,reg.preg(0)'length))));
        elsif rising_edge(clk) then
                reg <= reg_nxt;
        end if;
end process syn;

asyn : process (clk, reset, reg, psw_nxt, ext_reg, pwr_en, pinc, paddr)
	variable reg_nxt_v : gpm_internal;
	variable incb : ext_addr_t;
	variable sel_pval, sel_pval_nxt : ext_addr_t;
	
	variable data_out_v : gp_register_t;
	variable data_v : gp_register_t;
	variable tmp_data  : gp_register_t;
	
begin
	reg_nxt_v := reg;
	data_v  := ext_reg.data;

	psw <= reg.status;
	
	data_out_v := (others => '0');

	incb(0) := '1';
	if pinc = '1' then
		incb(incb'high downto 1) := (others => '1');
	else
		incb(incb'high downto 1) := (others => '0');
	end if;

	sel_pval:= reg_nxt_v.preg(0);
	sel_pval_nxt := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
	if pwr_en = '1' then
		reg_nxt_v.preg(0) := sel_pval_nxt;
	end if;

	reg_nxt_v.status := psw_nxt;
 	
	reg_nxt <= reg_nxt_v;
	data_out <= data_out_v;
	
	pval <= (others =>'0');
	pval(pval'high downto BYTEADDR) <= sel_pval;
	pval_nxt <= (others =>'0');
	pval_nxt(pval'high downto BYTEADDR) <= sel_pval_nxt;
end process asyn;

end behav;