cpu/src/execute_stage_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.alu_pkg.all;
   7 --use work.gpm_pkg.all;
   8 use work.extension_pkg.all;
   9
  10 architecture behav of execute_stage is
  11
  12 signal condition : condition_t;
  13 signal op_group : op_info_t;
  14 signal op_detail : op_opt_t;
  15 signal left_operand, right_operand : gp_register_t;
  16 signal alu_state, alu_nxt : alu_result_rec;
  17 signal psw : status_rec;
  18                 -- extension signals
  19                 signal ext_gpmp :  extmod_rec;
  20                 signal data_out    : gp_register_t;
  21
  22 signal pval : gp_register_t;
  23 signal paddr : paddr_t;
  24 signal pinc, pwr_en : std_logic;
  25
  26
  27
  28 type exec_internal is record
  29         result : gp_register_t;
  30         res_addr : gp_addr_t;
  31         alu_jump : std_logic;
  32         brpr    : std_logic;
  33         wr_en   : std_logic;
  34 end record;
  35
  36 signal reg, reg_nxt : exec_internal;
  37
  38 begin
  39
  40 alu_inst : alu
  41 port map(clk, reset, condition, op_group,
  42          left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, alu_nxt,addr,data, pinc, pwr_en, paddr);
  43
  44
  45
  46         gpmp_inst :  extension_gpm
  47                 generic map (RESET_VALUE)
  48                 port map (
  49                         clk,
  50                         reset,
  51                         ext_gpmp,
  52                         ext_data_out,
  53                         alu_nxt.status,
  54                         paddr,
  55                         pinc,
  56                         pwr_en,
  57                         psw,
  58                         pval
  59                 );
  60
  61
  62
  63 syn: process(clk, reset)
  64
  65 begin
  66
  67         if reset = RESET_VALUE then
  68                 reg.alu_jump <= '0';
  69                 reg.brpr <= '0';
  70                 reg.wr_en <= '0';
  71                 reg.result <= (others =>'0');
  72                 reg.res_addr <= (others => '0');
  73         elsif rising_edge(clk) then
  74                 reg <= reg_nxt;
  75         end if;
  76
  77 end process;
  78
  79 asyn: process(reset,dec_instr, alu_nxt, psw, reg,left_operand,right_operand)
  80 begin
  81
  82         condition <= dec_instr.condition;
  83         op_group <= dec_instr.op_group;
  84         op_detail <= dec_instr.op_detail;
  85
  86
  87
  88         alu_state <= (reg.result,dec_instr.daddr,psw,reg.alu_jump,reg.brpr,'0','0','0','0','0','0');
  89
  90
  91         if reset = RESET_VALUE then
  92                 condition <= COND_NEVER;
  93         else
  94
  95         end if;
  96
  97         reg_nxt.brpr <= alu_nxt.brpr;
  98         reg_nxt.alu_jump <= alu_nxt.alu_jump;
  99         reg_nxt.wr_en <= alu_nxt.reg_op;
 100         reg_nxt.result <= alu_nxt.result;
 101         reg_nxt.res_addr <= alu_nxt.result_addr;
 102
 103 end process asyn;
 104
 105 forward: process(regfile_val, reg_we, reg_addr, dec_instr)
 106 begin
 107         left_operand <= dec_instr.src1;
 108         right_operand <= dec_instr.src2;
 109
 110         if reg_we = '1' then
 111                 if dec_instr.saddr1 = reg_addr then
 112                         left_operand <= regfile_val;
 113                 end if;
 114                 if (dec_instr.saddr2 = reg_addr)  and  (dec_instr.op_detail(IMM_OPT) = '0') then
 115                         right_operand <= regfile_val;
 116                 end if;
 117         end if;
 118 end process forward;
 119
 120 result <= reg.result;
 121 result_addr <= reg.res_addr;
 122 alu_jump <= reg.alu_jump;
 123 brpr <= reg.brpr;
 124 wr_en <= reg.wr_en;
 125 dmem <= alu_nxt.mem_op;
 126 --dmem <= reg.result(4);
 127 dmem_write_en <= alu_nxt.mem_en;
 128 --dmem_write_en <= reg.result(0);
 129 --dmem_write_en <= '1';
 130 hword <= alu_nxt.hw_op;
 131 --hword <= reg.result(1);
 132 byte_s <= alu_nxt.byte_op;
 133
 134 --addr <= alu_nxt.result;
 135 --data <= right_operand;
 136 --byte_s <= reg.result(2);
 137 end behav;
 138