2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
8 architecture add_op of exec_op is
10 signal sub, addc : std_logic;
14 sub <= op_detail(SUB_OPT);
15 addc <= op_detail(CARRY_OPT);
17 calc: process(left_operand, right_operand, alu_state, sub, addc)
18 variable alu_result_v : alu_result_rec;
19 variable complement : gp_register_t;
20 variable carry_res : unsigned(gp_register_t'length downto 0);
21 variable tmp_right_operand : unsigned(gp_register_t'length downto 0);
22 variable oflo1, oflo2, l_neg, r_neg : std_logic;
23 variable addcarry : unsigned(carry_res'range);
25 alu_result_v := alu_state;
27 addcarry := (others =>'0');
28 addcarry(0) := alu_state.status.carry and addc;
30 complement := inc(not(right_operand));
31 l_neg := left_operand(gp_register_t'high);
33 carry_res := unsigned('0' & left_operand)+addcarry;
34 oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high));
37 tmp_right_operand := unsigned('0' & complement);
39 tmp_right_operand := unsigned('0' & right_operand);
42 l_neg := carry_res(gp_register_t'high);
43 r_neg := tmp_right_operand(gp_register_t'high);
45 carry_res := carry_res + tmp_right_operand;
46 oflo2 := add_oflo(l_neg,r_neg,carry_res(gp_register_t'high));
49 alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range));
50 alu_result_v.status.carry := carry_res(carry_res'high);
51 -- alu_result_v.result := (0 => '1', others => '0');
53 alu_result_v.status.oflo := oflo1 or oflo2;
55 --sign will be set globally.
56 --zero will be set globally.
58 alu_result <= alu_result_v;
61 end architecture add_op;