cpu/src/decode_stage_b.vhd

   1 library IEEE;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7 use work.core_pkg.all;
   8 use work.common_pkg.all;
   9
  10
  11
  12 architecture behav of decode_stage is
  13
  14 signal instr_spl : instruction_rec;
  15
  16 signal rtw_rec, rtw_rec_nxt : read_through_write_rec;
  17 signal reg1_mem_data, reg2_mem_data : gp_register_t;
  18
  19 begin
  20
  21         -- register file
  22         register_ram : r2_w_ram
  23                 generic map (
  24                         REG_ADDR_WIDTH,
  25                         WORD_WIDTH
  26                 )
  27
  28                 port map (
  29                         clk,
  30                         reg_w_addr,
  31                         instr_spl.reg_src1_addr,
  32                         instr_spl.reg_src2_addr,
  33                         reg_we,
  34                         reg_wr_data,
  35                         reg1_mem_data,
  36                         reg2_mem_data
  37                 );
  38
  39
  40         decoder_inst : decoder
  41
  42                 port map (
  43                         instruction,
  44                         instr_spl
  45                 );
  46
  47 -- sync process for read through write registers
  48 syn: process(clk, reset)
  49
  50 begin
  51
  52         if (reset = RESET_VALUE) then
  53                 rtw_rec.rtw_reg <= (others => '0');
  54                 rtw_rec.rtw_reg1 <= '0';
  55                 rtw_rec.rtw_reg2 <= '0';
  56         elsif rising_edge(clk) then
  57                 rtw_rec <= rtw_rec_nxt;
  58         end if;
  59
  60 end process;
  61
  62
  63 -- async process: decides between memory and read-through-write buffer on output
  64 output: process(rtw_rec, reg1_mem_data, reg2_mem_data)
  65
  66 begin
  67         if (rtw_rec.rtw_reg1 = '1') then
  68                 reg1_rd_data <= rtw_rec.rtw_reg;
  69         else
  70                 reg1_rd_data <= reg1_mem_data;
  71         end if;
  72
  73         if (rtw_rec.rtw_reg2 = '1') then
  74                 reg2_rd_data <= rtw_rec.rtw_reg;
  75         else
  76                 reg2_rd_data <= reg2_mem_data;
  77         end if;
  78 end process;
  79
  80
  81 -- async process: checks forward condition
  82 forward: process(instr_spl, reg_w_addr, reg_wr_data)
  83
  84 begin
  85
  86         rtw_rec_nxt.rtw_reg <= reg_wr_data;
  87         rtw_rec_nxt.rtw_reg1 <= '0';
  88         rtw_rec_nxt.rtw_reg2 <= '0';
  89
  90         if (reg_w_addr = instr_spl.reg_src1_addr) then
  91                 rtw_rec_nxt.rtw_reg1 <= '1';
  92         end if;
  93
  94         if (reg_w_addr = instr_spl.reg_src2_addr) then
  95                 rtw_rec_nxt.rtw_reg2 <= '1';
  96         end if;
  97
  98 end process;
  99
 100
 101 -- async process: calculates branch prediction
 102 br_pred: process(instr_spl)
 103
 104 begin
 105
 106         branch_prediction_res <= (others => '0');
 107         branch_prediction_bit <= '0';
 108
 109         if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
 110                 branch_prediction_res <= instr_spl.immediate;   --both 32 bit
 111                 branch_prediction_bit <= '1';
 112         end if;
 113
 114 end process;
 115
 116 end behav;
 117