library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.mem_pkg.all;
use work.core_pkg.all;
use work.common_pkg.all;



architecture behav of decode_stage is

signal instr_spl : instruction_rec;

signal rtw_rec, rtw_rec_nxt : read_through_write_rec;
signal reg1_mem_data, reg2_mem_data : gp_register_t;

begin

	-- register file
	register_ram : r2_w_ram
		generic map (
			REG_ADDR_WIDTH,
			WORD_WIDTH
		)
		
		port map (
			clk,
			reg_w_addr,
			instr_spl.reg_src1_addr,
			instr_spl.reg_src2_addr,
			reg_we,
			reg_wr_data,
			reg1_mem_data,
			reg2_mem_data
		);


	decoder_inst : decoder

		port map (
			instruction, 
			instr_spl
		);

-- sync process for read through write registers
syn: process(clk, reset)

begin

	if (reset = RESET_VALUE) then
		rtw_rec.rtw_reg <= (others => '0');
		rtw_rec.rtw_reg1 <= '0';
		rtw_rec.rtw_reg2 <= '0';
	elsif rising_edge(clk) then
		rtw_rec <= rtw_rec_nxt;
	end if;
	
end process; 


-- async process: decides between memory and read-through-write buffer on output
output: process(rtw_rec, reg1_mem_data, reg2_mem_data)

begin
	if (rtw_rec.rtw_reg1 = '1') then
		reg1_rd_data <= rtw_rec.rtw_reg;
	else
		reg1_rd_data <= reg1_mem_data;
	end if;

	if (rtw_rec.rtw_reg2 = '1') then
		reg2_rd_data <= rtw_rec.rtw_reg;
	else
		reg2_rd_data <= reg2_mem_data;
	end if;
end process;


-- async process: checks forward condition
forward: process(instr_spl, reg_w_addr, reg_wr_data)

begin

	rtw_rec_nxt.rtw_reg <= reg_wr_data;
	rtw_rec_nxt.rtw_reg1 <= '0';
	rtw_rec_nxt.rtw_reg2 <= '0';

	if (reg_w_addr = instr_spl.reg_src1_addr) then
		rtw_rec_nxt.rtw_reg1 <= '1';
	end if;

	if (reg_w_addr = instr_spl.reg_src2_addr) then
		rtw_rec_nxt.rtw_reg2 <= '1';
	end if;

end process;


-- async process: calculates branch prediction
br_pred: process(instr_spl)

begin

	branch_prediction_res <= (others => '0');
	branch_prediction_bit <= '0';

	if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
		branch_prediction_res <= instr_spl.immediate;	--both 32 bit
		branch_prediction_bit <= '1';
	end if;

end process;

end behav;