2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
9 entity core_top_c2de1 is
13 sys_res : in std_logic;
14 soft_res : in std_logic;
15 sys_clk : in std_logic;
16 -- result : out gp_register_t;
17 -- reg_wr_data : out gp_register_t
19 bus_tx : out std_logic;
20 bus_rx : in std_logic;
23 sseg0 : out std_logic_vector(0 to 6);
24 sseg1 : out std_logic_vector(0 to 6);
25 sseg2 : out std_logic_vector(0 to 6);
26 sseg3 : out std_logic_vector(0 to 6)
31 architecture behav of core_top_c2de1 is
33 constant SYNC_STAGES : integer := 2;
34 constant RESET_VALUE : std_logic := '0';
36 signal jump_result : instruction_addr_t;
37 signal jump_result_pin : instruction_addr_t;
38 signal prediction_result_pin : instruction_addr_t;
39 signal branch_prediction_bit_pin : std_logic;
40 signal alu_jump_bit_pin : std_logic;
41 signal instruction_pin : instruction_word_t;
42 signal prog_cnt_pin : instruction_addr_t;
44 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
45 signal reg_wr_data_pin : gp_register_t;
46 signal reg_we_pin : std_logic;
47 signal to_next_stage : dec_op;
49 signal result_pin : gp_register_t;--reg
50 signal result_addr_pin : gp_addr_t;--reg
51 signal addr_pin : word_t; --memaddr
52 signal data_pin : gp_register_t; --mem data --ureg
53 signal alu_jump_pin : std_logic;--reg
54 signal brpr_pin : std_logic; --reg
55 signal wr_en_pin : std_logic;--regop --reg
56 signal dmem_pin : std_logic;--memop
57 signal dmem_wr_en_pin : std_logic;
58 signal hword_pin : std_logic;
59 signal byte_s_pin : std_logic;
61 signal gpm_in_pin : extmod_rec;
62 signal gpm_out_pin : gp_register_t;
63 signal nop_pin : std_logic;
65 signal sync : std_logic_vector(1 to SYNC_STAGES);
66 signal sync2 : std_logic_vector(1 to SYNC_STAGES);
67 signal sys_res_n, soft_res_n : std_logic;
69 signal int_req : interrupt_t;
71 signal new_im_data : std_logic;
72 signal im_addr, im_data : gp_register_t;
73 -- signal led2 : std_logic;
75 signal vers, vers_nxt : exec2wb_rec;
78 fetch_st : fetch_stage
87 clk => sys_clk, --: in std_logic;
88 reset => sys_res_n, --: in std_logic;
89 s_reset => soft_res_n,
92 jump_result => jump_result_pin, --: in instruction_addr_t;
93 prediction_result => prediction_result_pin, --: in instruction_addr_t;
94 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
95 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
97 -- instruction memory program port :D
98 new_im_data_in => new_im_data,
102 instruction => instruction_pin, --: out instruction_word_t
103 prog_cnt => prog_cnt_pin,
107 decode_st : decode_stage
109 -- active reset value
111 -- active logic value
117 clk => sys_clk, --: in std_logic;
118 reset => sys_res_n and soft_res_n, -- : in std_logic;
121 instruction => instruction_pin, --: in instruction_word_t;
122 prog_cnt => prog_cnt_pin,
123 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
124 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
125 reg_we => reg_we_pin, --: in std_logic;
129 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
130 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
131 to_next_stage => to_next_stage
134 exec_st : execute_stage
135 generic map(RESET_VALUE)
136 port map(sys_clk, sys_res_n and soft_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
137 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
140 writeback_st : writeback_stage
141 generic map(RESET_VALUE, '1', "altera", 434)
142 port map(sys_clk, sys_res_n and soft_res_n, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
143 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
144 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
145 new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req);
149 syn: process(sys_clk, sys_res)
153 if sys_res = RESET_VALUE then
155 sync <= (others => RESET_VALUE);
157 elsif rising_edge(sys_clk) then
159 for i in 2 to SYNC_STAGES loop
160 sync(i) <= sync(i - 1);
163 sync2(1) <= soft_res;
164 for i in 2 to SYNC_STAGES loop
165 sync2(i) <= sync2(i - 1);
172 sys_res_n <= sync(SYNC_STAGES);
173 soft_res_n <= sync2(SYNC_STAGES);
174 nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
175 jump_result <= prog_cnt_pin; --jump_result_pin;