cpu/src/core_top.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 entity core_top is
   9
  10         port(
  11                 --System input pins
  12                         sys_clk : in std_logic;
  13                         sys_res : in std_logic;
  14                         result : out gp_register_t;
  15                         jump_result : out instruction_addr_t;
  16                         reg_wr_data : out gp_register_t
  17
  18                 );
  19
  20 end core_top;
  21
  22 architecture behav of core_top is
  23
  24                 signal jump_result_pin : instruction_addr_t;
  25                 signal prediction_result_pin : instruction_addr_t;
  26                 signal branch_prediction_bit_pin : std_logic;
  27                 signal alu_jump_bit_pin : std_logic;
  28                 signal instruction_pin : instruction_word_t;
  29                 signal prog_cnt_pin : instruction_addr_t;
  30
  31                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  32                 signal reg_wr_data_pin : gp_register_t;
  33                 signal reg_we_pin : std_logic;
  34                 signal to_next_stage : dec_op;
  35
  36 --              signal reg1_rd_data_pin : gp_register_t;
  37 --              signal reg2_rd_data_pin : gp_register_t;
  38
  39                  signal result_pin : gp_register_t;--reg
  40                  signal result_addr_pin : gp_addr_t;--reg
  41                  signal addr_pin : word_t; --memaddr
  42                  signal data_pin : gp_register_t; --mem data --ureg
  43                  signal alu_jump_pin : std_logic;--reg
  44                  signal brpr_pin  : std_logic;  --reg
  45                  signal wr_en_pin : std_logic;--regop --reg
  46                  signal dmem_pin  : std_logic;--memop
  47                  signal dmem_wr_en_pin : std_logic;
  48                  signal hword_pin  : std_logic;
  49                  signal byte_s_pin : std_logic;
  50
  51                                  signal gpm_in_pin : ext_mod_rec;
  52                                  signal gpm_out_pin : gp_register_t;
  53                  signal nop_pin : std_logic;
  54
  55
  56 begin
  57
  58         fetch_st : fetch_stage
  59                 generic map (
  60
  61                         '0',
  62                         '1'
  63                 )
  64
  65                 port map (
  66                 --System inputs
  67                         clk => sys_clk, --: in std_logic;
  68                         reset => sys_res, --: in std_logic;
  69
  70                 --Data inputs
  71                         jump_result => jump_result_pin, --: in instruction_addr_t;
  72                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  73                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  74                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  75
  76                 --Data outputs
  77                         instruction => instruction_pin, --: out instruction_word_t
  78                         prog_cnt => prog_cnt_pin
  79                 );
  80
  81         decode_st : decode_stage
  82                 generic map (
  83                         -- active reset value
  84                         '0',
  85                         -- active logic value
  86                         '1'
  87
  88                         )
  89                 port map (
  90                 --System inputs
  91                         clk => sys_clk, --: in std_logic;
  92                         reset => sys_res, -- : in std_logic;
  93
  94                 --Data inputs
  95                         instruction => instruction_pin, --: in instruction_word_t;
  96                         prog_cnt => prog_cnt_pin,
  97                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  98                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
  99                         reg_we => reg_we_pin, --: in std_logic;
 100                         nop => nop_pin,
 101
 102                 --Data outputs
 103                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 104                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 105                         to_next_stage => to_next_stage
 106                 );
 107
 108           exec_st : execute_stage
 109                 generic map('0')
 110                 port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
 111                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 112
 113           writeback_st : writeback_stage
 114                 generic map('0', '1')
 115                 port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 116                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 117                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
 118
 119
 120
 121
 122
 123 --init : process(all)
 124
 125 --begin
 126 --      jump_result_pin <= (others => '0');
 127 --      alu_jump_bit_pin <= '0';
 128 --      reg_w_addr_pin <= (others => '0');
 129 --      reg_wr_data_pin <= (others => '0');
 130 --      reg_we_pin <= '0';
 131
 132 --end process;
 133
 134         result <= result_pin;
 135         nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
 136
 137         jump_result <= jump_result_pin;
 138
 139         reg_wr_data <= reg_wr_data_pin;
 140 end behav;