2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
12 sys_clk : in std_logic;
13 sys_res : in std_logic;
15 to_next_stage : out dec_op
21 architecture behav of core_top is
23 signal jump_result_pin : instruction_addr_t;
24 signal prediction_result_pin : instruction_addr_t;
25 signal branch_prediction_bit_pin : std_logic;
26 signal alu_jump_bit_pin : std_logic;
27 signal instruction_pin : instruction_word_t;
29 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
30 signal reg_wr_data_pin : gp_register_t;
31 signal reg_we_pin : std_logic;
33 -- signal reg1_rd_data_pin : gp_register_t;
34 -- signal reg2_rd_data_pin : gp_register_t;
39 fetch_st : fetch_stage
48 clk => sys_clk, --: in std_logic;
49 reset => sys_res, --: in std_logic;
52 jump_result => jump_result_pin, --: in instruction_addr_t;
53 prediction_result => prediction_result_pin, --: in instruction_addr_t;
54 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
55 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
58 instruction => instruction_pin --: out instruction_word_t
61 decode_st : decode_stage
71 clk => sys_clk, --: in std_logic;
72 reset => sys_res, -- : in std_logic;
75 instruction => instruction_pin, --: in instruction_word_t;
76 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
77 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
78 reg_we => reg_we_pin, --: in std_logic;
81 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
82 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
83 to_next_stage => to_next_stage
90 jump_result_pin <= (others => '0');
91 alu_jump_bit_pin <= '0';
92 reg_w_addr_pin <= (others => '0');
93 reg_wr_data_pin <= (others => '0');