2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
12 sys_clk : in std_logic;
13 sys_res : in std_logic;
14 result : out gp_register_t;
15 jump_result : out instruction_addr_t;
16 reg_wr_data : out gp_register_t
22 architecture behav of core_top is
24 signal jump_result_pin : instruction_addr_t;
25 signal prediction_result_pin : instruction_addr_t;
26 signal branch_prediction_bit_pin : std_logic;
27 signal alu_jump_bit_pin : std_logic;
28 signal instruction_pin : instruction_word_t;
30 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
31 signal reg_wr_data_pin : gp_register_t;
32 signal reg_we_pin : std_logic;
33 signal to_next_stage : dec_op;
35 -- signal reg1_rd_data_pin : gp_register_t;
36 -- signal reg2_rd_data_pin : gp_register_t;
38 signal result_pin : gp_register_t;--reg
39 signal result_addr_pin : gp_addr_t;--reg
40 signal addr_pin : word_t; --memaddr
41 signal data_pin : gp_register_t; --mem data --ureg
42 signal alu_jump_pin : std_logic;--reg
43 signal brpr_pin : std_logic; --reg
44 signal wr_en_pin : std_logic;--regop --reg
45 signal dmem_pin : std_logic;--memop
46 signal dmem_wr_en_pin : std_logic;
47 signal hword_pin : std_logic;
48 signal byte_s_pin : std_logic;
49 signal nop_pin : std_logic;
55 fetch_st : fetch_stage
64 clk => sys_clk, --: in std_logic;
65 reset => sys_res, --: in std_logic;
68 jump_result => jump_result_pin, --: in instruction_addr_t;
69 prediction_result => prediction_result_pin, --: in instruction_addr_t;
70 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
71 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
74 instruction => instruction_pin --: out instruction_word_t
77 decode_st : decode_stage
87 clk => sys_clk, --: in std_logic;
88 reset => sys_res, -- : in std_logic;
91 instruction => instruction_pin, --: in instruction_word_t;
92 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
93 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
94 reg_we => reg_we_pin, --: in std_logic;
98 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
99 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
100 to_next_stage => to_next_stage
103 exec_st : execute_stage
105 port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
106 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
108 writeback_st : writeback_stage
109 generic map('0', '1')
110 port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
111 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
112 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
118 --init : process(all)
121 -- jump_result_pin <= (others => '0');
122 -- alu_jump_bit_pin <= '0';
123 -- reg_w_addr_pin <= (others => '0');
124 -- reg_wr_data_pin <= (others => '0');
125 -- reg_we_pin <= '0';
129 result <= result_pin;
130 nop_pin <= (alu_jump_bit_pin xor brpr_pin);
132 jump_result <= jump_result_pin;
134 reg_wr_data <= reg_wr_data_pin;