3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
10 constant WORD_WIDTH : INTEGER := 32;
11 constant HWORD_WIDTH : INTEGER := 16;
12 constant BYTE_WIDTH : INTEGER := 8;
13 constant OPCODE_WIDTH : INTEGER := 5;
14 constant DISPL_WIDTH : INTEGER := 15;
16 subtype byte_t is std_logic_vector(BYTE_WIDTH-1 downto 0);
17 subtype hword_t is std_logic_vector(HWORD_WIDTH-1 downto 0);
18 subtype word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
20 subtype gp_register_t is word_t;
22 subtype byte_en_t is std_logic_vector((gp_register_t'length/byte_t'length-1) downto 0);
24 constant REG_ZERO : gp_register_t := (others => '0');
26 constant INSTR_ADDR_WIDTH : INTEGER := 32;
27 constant PHYS_INSTR_ADDR_WIDTH : INTEGER := 10;
28 constant ROM_INSTR_ADDR_WIDTH : INTEGER := 7;
29 constant REG_ADDR_WIDTH : INTEGER := 4;
30 constant DATA_ADDR_WIDTH : INTEGER := 10;
31 constant PHYS_DATA_ADDR_WIDTH : INTEGER := 32;
33 constant NUM_OP_OPT_WIDTH : INTEGER := 6;
34 constant COND_WIDTH : INTEGER := 4;
35 constant DATA_END_ADDR : integer := ((2**DATA_ADDR_WIDTH)-1);
37 constant ROM_USE : std_logic := '1';
38 constant RAM_USE : std_logic := '0';
40 subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
41 subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0);
42 subtype instr_addr_t is instruction_addr_t;
44 subtype gp_addr_t is std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
45 subtype data_ram_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
46 subtype data_ram_addr_t is std_logic_vector(DATA_ADDR_WIDTH-1 downto 0);
48 subtype opcode_t is std_logic_vector(OPCODE_WIDTH-1 downto 0);
49 subtype condition_t is std_logic_vector(COND_WIDTH-1 downto 0);
51 --Opcode consits of decoded group information type and option bits
52 --currently not complete, might need option increase too.
53 --IMMEDIATE always in right_operand (src2)
55 constant IMM_OPT : integer := 0; -- no sharing
57 constant SUB_OPT : integer := 1;
58 constant ARITH_OPT : integer := 1;
59 constant HWORD_OPT : integer := 1;
60 constant PUSH_OPT : integer := 1;
61 constant LOW_HIGH_OPT : integer := 1;
62 constant DIRECT_JUMP_OPT : integer := 1;
64 constant CARRY_OPT : integer := 2;
65 constant BYTE_OPT : integer := 2;
66 constant LDI_REPLACE_OPT : integer := 2;
67 constant PWREN_OPT : integer := 2;
69 constant RIGHT_OPT : integer := 3;
70 constant JMP_REG_OPT : integer := 3;
71 constant ST_OPT : integer := 3; -- store opt
72 constant RET_OPT : integer := 3;
74 constant NO_PSW_OPT : integer := 4;--no sharing
75 constant NO_DST_OPT : integer := 5; --no sharing
77 type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP, LDST_OP, JMP_OP, JMP_ST_OP, STACK_OP);
78 subtype op_opt_t is std_logic_vector(NUM_OP_OPT_WIDTH-1 downto 0);
80 type interrupt_t is (IDLE, UART);
82 constant UART_INT_EN_BIT : integer := 1;
83 constant GLOBAL_INT_EN_BIT : integer := 0;
85 constant UART_INT_VECTOR : std_logic_vector(PHYS_INSTR_ADDR_WIDTH-1 downto 0) := (0 => '1', others => '0');
87 type instruction_rec is record
89 predicates : std_logic_vector(3 downto 0);
93 reg_dest_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
94 reg_src1_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
95 reg_src2_addr : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
97 immediate : std_logic_vector(WORD_WIDTH-1 downto 0);
99 displacement : gp_register_t;
101 jmptype : std_logic_vector(1 downto 0);
103 high_low, fill, signext, bp, int: std_logic;
105 op_detail : op_opt_t;
106 op_group : op_info_t;
112 type read_through_write_rec is record
114 rtw_reg : gp_register_t;
115 rtw_reg1 : std_logic;
116 rtw_reg2 : std_logic;
117 immediate : gp_register_t;
119 reg1_addr : gp_addr_t;
120 reg2_addr : gp_addr_t;
124 type dec_op is record
125 condition : condition_t;
126 op_group : op_info_t;
127 op_detail : op_opt_t;
130 displacement : gp_register_t;
131 prog_cnt : instr_addr_t;
133 src1 : gp_register_t;
134 src2 : gp_register_t;
143 type writeback_rec is record
144 -- result : in gp_register_t; --reg (alu result or jumpaddr)
145 -- result_addr : in gp_addr_t; --reg
146 address : word_t; --ureg
147 -- alu_jmp : in std_logic; --reg
148 -- br_pred : in std_logic; --reg
149 -- write_en : in std_logic; --reg (register file)
150 dmem_en : std_logic; --ureg (jump addr in mem or in address)
151 dmem_write_en : std_logic; --ureg
152 hword : std_logic; --ureg
155 data : gp_register_t;
158 type exec2wb_rec is record
159 result : gp_register_t; --reg (alu result or jumpaddr)
160 result_addr : gp_addr_t; --reg
161 address : word_t; --ureg
162 ram_data : word_t; --ureg
163 alu_jmp : std_logic; --reg
164 br_pred : std_logic; --reg
165 write_en : std_logic; --reg (register file) bei jump 1 wenn addr in result
166 dmem_en : std_logic; --ureg (jump addr in mem or in address)
167 dmem_write_en : std_logic; --ureg
168 hword : std_logic; --ureg
169 byte_s : std_logic; --ureg
172 function inc(value : in std_logic_vector; constant by : in integer := 1) return std_logic_vector;
173 function log2c(constant value : in integer range 0 to integer'high) return integer;
174 end package common_pkg;
176 package body common_pkg is
178 function inc(value : in std_logic_vector; constant by : in integer := 1) return std_logic_vector is
180 return std_logic_vector(UNSIGNED(value)+by);
183 function log2c(constant value : in integer range 0 to integer'high) return integer is
184 variable ret_value : integer;
185 variable cur_value : integer;
190 while cur_value < value loop
191 ret_value := ret_value + 1;
192 cur_value := cur_value * 2;
197 end package body common_pkg;