2 use IEEE.std_logic_1164.all;
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3 use IEEE.numeric_std.all;
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5 use work.alu_pkg.all;
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8 architecture behaviour of alu is
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14 reset : in std_logic;
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16 left_operand : in gp_register_t;
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17 right_operand : in gp_register_t;
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18 op_detail : in op_opt_t;
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19 alu_state : in alu_result_rec;
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20 alu_result : out alu_result_rec
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22 end component exec_op;
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24 signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
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25 signal left_o, right_o : gp_register_t;
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29 add_inst : entity work.exec_op(add_op)
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30 port map(clk,reset,left_o, right_o, op_detail, alu_state, add_result);
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32 and_inst : entity work.exec_op(and_op)
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33 port map(clk,reset,left_o, right_o, op_detail, alu_state, and_result);
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35 or_inst : entity work.exec_op(or_op)
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36 port map(clk,reset,left_o, right_o, op_detail, alu_state, or_result);
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38 xor_inst : entity work.exec_op(xor_op)
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39 port map(clk,reset,left_o, right_o, op_detail, alu_state, xor_result);
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41 shift_inst : entity work.exec_op(shift_op)
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42 port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);
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44 calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval)
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45 variable result_v : alu_result_rec;
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46 variable res_prod : std_logic;
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47 variable cond_met : std_logic;
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48 variable mem_en : std_logic;
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49 variable mem_op : std_logic;
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50 variable alu_jump : std_logic;
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51 variable nop : std_logic;
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53 result_v := alu_state;
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60 left_o <= left_operand;
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61 right_o <= right_operand;
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63 addr <= add_result.result;
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64 data <= right_operand;
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68 paddr <= (others =>'0');
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70 result_v.result := add_result.result;
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74 cond_met := not(alu_state.status.zero);
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76 cond_met := alu_state.status.zero;
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78 cond_met := not(alu_state.status.oflo);
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80 cond_met := alu_state.status.oflo;
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82 cond_met := not(alu_state.status.carry);
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84 cond_met := alu_state.status.carry;
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86 cond_met := not(alu_state.status.sign);
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88 cond_met := alu_state.status.sign;
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90 cond_met := not(alu_state.status.carry) and not(alu_state.status.zero);
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92 cond_met := alu_state.status.carry or alu_state.status.zero;
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94 cond_met := not(alu_state.status.sign xor alu_state.status.oflo);
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96 cond_met := alu_state.status.sign xor alu_state.status.oflo;
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98 cond_met := not(alu_state.status.zero) and not(alu_state.status.sign xor alu_state.status.oflo);
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100 cond_met := alu_state.status.zero or (alu_state.status.sign xor alu_state.status.oflo);
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101 when COND_ALWAYS =>
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105 when others => null;
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108 nop := (alu_state.alu_jump xnor alu_state.brpr);
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109 cond_met := cond_met and nop;
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113 result_v := add_result;
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115 result_v := and_result;
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117 result_v := or_result;
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119 result_v := xor_result;
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121 result_v := shift_result;
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125 if op_detail(IMM_OPT) = '1' then
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126 result_v.result := right_operand;
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130 if op_detail(ST_OPT) = '1' then
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131 right_o <= displacement;
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135 if op_detail(JMP_REG_OPT) = '0' then
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136 left_o <= prog_cnt;
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139 when JMP_ST_OP => null;
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144 result_v.status.zero := '0';
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145 if result_v.result = REG_ZERO then
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146 result_v.status.zero := '1';
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149 result_v.status.sign := result_v.result(gp_register_t'high);
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151 if (op_detail(NO_PSW_OPT) = '1') or (cond_met = '0') then
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152 result_v.status := alu_state.status;
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155 result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;
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156 result_v.mem_en := mem_en and cond_met;
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157 result_v.mem_op := mem_op and cond_met;
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158 result_v.alu_jump := alu_jump and cond_met;
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159 result_v.brpr := brpr and nop;
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161 if (result_v.alu_jump = '0') and (brpr = '1') then
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162 result_v.result := (others => '0');
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163 result_v.result(prog_cnt'range) := std_logic_vector(unsigned(prog_cnt)+1);
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164 --result_v.reg_op := '1';
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167 alu_result <= result_v;
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171 end architecture behaviour;
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