cpu/sim/testcore1.do

   1 vlib work
   2 vmap work work
   3
   4 vcom -work work ../src/mem_pkg.vhd
   5 vcom -work work ../src/rom.vhd
   6 vcom -work work ../src/rom_b.vhd
   7 vcom -work work ../src/r_w_ram.vhd
   8 vcom -work work ../src/r_w_ram_be.vhd
   9 vcom -work work ../src/r_w_ram_be_b.vhd
  10 vcom -work work ../src/r_w_ram_b.vhd
  11 vcom -work work ../src/r2_w_ram.vhd
  12 vcom -work work ../src/r2_w_ram_b.vhd
  13 vcom -work work ../src/common_pkg.vhd
  14 vcom -work work ../src/extension_pkg.vhd
  15 vcom -work work ../src/core_pkg.vhd
  16 vcom -work work ../src/decoder.vhd
  17 vcom -work work ../src/decoder_b.vhd
  18 vcom -work work ../src/fetch_stage.vhd
  19 vcom -work work ../src/fetch_stage_b.vhd
  20 vcom -work work ../src/decode_stage.vhd
  21 vcom -work work ../src/decode_stage_b.vhd
  22
  23 vcom -work work ../src/alu_pkg.vhd
  24
  25
  26 vcom -work work ../src/exec_op.vhd
  27 vcom -work work ../src/exec_op/add_op_b.vhd
  28 vcom -work work ../src/exec_op/and_op_b.vhd
  29 vcom -work work ../src/exec_op/or_op_b.vhd
  30 vcom -work work ../src/exec_op/xor_op_b.vhd
  31 vcom -work work ../src/exec_op/shift_op_b.vhd
  32
  33 vcom -work work ../src/alu.vhd
  34 vcom -work work ../src/alu_b.vhd
  35
  36 vcom -work work ../src/gpm.vhd
  37 vcom -work work ../src/gpm_b.vhd
  38
  39 vcom -work work ../src/extension_pkg.vhd
  40 vcom -work work ../src/extension.vhd
  41 vcom -work work ../src/extension_b.vhd
  42
  43
  44 vcom -work work ../src/extension_imp_pkg.vhd
  45 vcom -work work ../src/extension_imp.vhd
  46 vcom -work work ../src/extension_imp_b.vhd
  47
  48 vcom -work work ../src/extension_7seg_pkg.vhd
  49 vcom -work work ../src/extension_7seg.vhd
  50 vcom -work work ../src/extension_7seg_b.vhd
  51
  52 vcom -work work ../src/extension_timer_pkg.vhd
  53 vcom -work work ../src/extension_timer.vhd
  54 vcom -work work ../src/extension_timer_b.vhd
  55
  56 vcom -work work ../src/extension_uart_pkg.vhd
  57 vcom -work work ../src/rs232_tx.vhd
  58 vcom -work work ../src/rs232_tx_arc.vhd
  59 vcom -work work ../src/rs232_rx.vhd
  60 vcom -work work ../src/rs232_rx_arc.vhd
  61 vcom -work work ../src/extension_uart.vhd
  62 vcom -work work ../src/extension_uart_b.vhd
  63
  64 vcom -work work ../src/execute_stage.vhd
  65 vcom -work work ../src/execute_stage_b.vhd
  66
  67
  68 vcom -work work ../src/writeback_stage.vhd
  69 vcom -work work ../src/writeback_stage_b.vhd
  70
  71 vcom -work work ../src/pipeline_tb.vhd
  72
  73 vsim work.pipeline_conf_beh -t ns
  74
  75 add wave  -group system -format logic /pipeline_tb/sys_clk_pin
  76 add wave  -group system -format logic /pipeline_tb/sys_res_n_pin
  77
  78 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr_nxt
  79 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr
  80 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_rd_data
  81 add wave  -group fetchstageregister -radix hexadecimal /pipeline_tb/fetch_st/instruction
  82 add wave  -group fetchstage -format logic /pipeline_tb/fetch_st/branch_prediction_bit
  83 add wave  -group fetchstage -format logic /pipeline_tb/fetch_st/rom_ram
  84 add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
  85
  86 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instruction
  87 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl
  88 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_dest_addr
  89 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_src1_addr
  90 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_src2_addr
  91
  92 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_we
  93 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
  94 add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
  95
  96
  97
  98
  99 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
 100 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
 101 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec
 102 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec.rtw_reg1
 103 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec.rtw_reg2
 104 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
 105 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage.src1
 106 add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage.src2
 107
 108
 109
 110
 111
 112
 113 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr
 114 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.daddr
 115 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.saddr1
 116 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.saddr2
 117 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.src1
 118 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.src2
 119 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_we
 120 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_addr
 121 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/regfile_val
 122 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/alu_inst/left_operand
 123 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/alu_inst/right_operand
 124 add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_nxt
 125
 126
 127 add wave  -group execstageregister -radix hexadecimal /pipeline_tb/exec_st/gpmp_inst/psw
 128 add wave  -group execstageregister -radix hexadecimal /pipeline_tb/exec_st/reg
 129 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/result
 130 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/result_addr
 131 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
 132 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/br_pred
 133 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/write_en
 134 add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/address
 135
 136 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_we
 137 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
 138 add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
 139
 140 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bus_rx
 141 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bus_tx
 142 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co
 143 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co_nxt
 144 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w2_uart_config
 145 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w3_uart_send
 146 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w4_uart_receive
 147 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/uart_data_read_nxt
 148 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg.sel
 149 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_rx_inst/rx_data_nxt
 150
 151 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w1_st_co
 152 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w1_st_co_nxt
 153 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w2_im_val
 154 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/timer/w2_im_val_nxt
 155
 156 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/reg_we
 157 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/write_en
 158 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_en
 159 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_write_en
 160 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_anysel
 161 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
 162 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.address
 163 add wave  -group test -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
 164 add wave  -group test -radix hexadecimal /pipeline_tb/exec_st/dmem_write_en
 165
 166 run 100000 ns