2 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
3 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
4 * Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
7 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
8 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
10 * Permission is hereby granted to use or copy this program
11 * for any purpose, provided the above notices are retained on all copies.
12 * Permission to modify the code and to distribute modified code is granted,
13 * provided the above notices are retained, and a notice that the code was
14 * modified is included with the above copyright notice.
16 * Some of the machine specific code was borrowed from our GC distribution.
19 /* The following really assume we have a 486 or better. Unfortunately */
20 /* gcc doesn't define a suitable feature test macro based on command */
22 /* We should perhaps test dynamically. */
24 #include "../all_aligned_atomic_load_store.h"
26 /* Real X86 implementations, except for some old WinChips, appear */
27 /* to enforce ordering between memory operations, EXCEPT that a later */
28 /* read can pass earlier writes, presumably due to the visible */
29 /* presence of store buffers. */
30 /* We ignore both the WinChips, and the fact that the official specs */
31 /* seem to be much weaker (and arguably too weak to be usable). */
33 #include "../ordered_except_wr.h"
35 #include "../test_and_set_t_is_char.h"
37 #if defined(AO_USE_PENTIUM4_INSTRS)
41 __asm__ __volatile__("mfence" : : : "memory");
44 #define AO_HAVE_nop_full
48 /* We could use the cpuid instruction. But that seems to be slower */
49 /* than the default implementation based on test_and_set_full. Thus */
50 /* we omit that bit of misinformation here. */
54 /* As far as we can tell, the lfence and sfence instructions are not */
55 /* currently needed or useful for cached memory accesses. */
57 /* Really only works for 486 and later */
59 AO_fetch_and_add_full (volatile AO_t *p, AO_t incr)
63 __asm__ __volatile__ ("lock; xaddq %0, %1" :
64 "=r" (result), "=m" (*p) : "0" (incr), "m" (*p)
69 #define AO_HAVE_fetch_and_add_full
71 AO_INLINE unsigned char
72 AO_char_fetch_and_add_full (volatile unsigned char *p, unsigned char incr)
76 __asm__ __volatile__ ("lock; xaddb %0, %1" :
77 "=q" (result), "=m" (*p) : "0" (incr), "m" (*p)
82 #define AO_HAVE_char_fetch_and_add_full
84 AO_INLINE unsigned short
85 AO_short_fetch_and_add_full (volatile unsigned short *p, unsigned short incr)
87 unsigned short result;
89 __asm__ __volatile__ ("lock; xaddw %0, %1" :
90 "=r" (result), "=m" (*p) : "0" (incr), "m" (*p)
95 #define AO_HAVE_short_fetch_and_add_full
97 AO_INLINE unsigned short
98 AO_int_fetch_and_add_full (volatile unsigned int *p, unsigned int incr)
102 __asm__ __volatile__ ("lock; xaddl %0, %1" :
103 "=r" (result), "=m" (*p) : "0" (incr), "m" (*p)
108 #define AO_HAVE_int_fetch_and_add_full
110 /* Really only works for 486 and later */
112 AO_or_full (volatile AO_t *p, AO_t incr)
114 __asm__ __volatile__ ("lock; orq %1, %0" :
115 "=m" (*p) : "r" (incr), "m" (*p) : "memory");
118 #define AO_HAVE_or_full
120 AO_INLINE AO_TS_VAL_t
121 AO_test_and_set_full(volatile AO_TS_t *addr)
123 unsigned char oldval;
124 /* Note: the "xchg" instruction does not need a "lock" prefix */
125 __asm__ __volatile__("xchgb %0, %1"
126 : "=q"(oldval), "=m"(*addr)
127 : "0"(0xff), "m"(*addr) : "memory");
128 return (AO_TS_VAL_t)oldval;
131 #define AO_HAVE_test_and_set_full
133 /* Returns nonzero if the comparison succeeded. */
135 AO_compare_and_swap_full(volatile AO_t *addr,
136 AO_t old, AO_t new_val)
139 __asm__ __volatile__("lock; cmpxchgq %3, %0; setz %1"
140 : "=m"(*addr), "=q"(result)
141 : "m"(*addr), "r" (new_val), "a"(old) : "memory");
145 #define AO_HAVE_compare_and_swap_full
147 /* FIXME: The Intel version has a 16byte CAS instruction. */