pci1x2x: remove latency/bridge control/cacheline size settings
[coreboot.git] / src / southbridge / ti /
drwxr-xr-x   ..
-rw-r--r-- 893 Kconfig
-rw-r--r-- 923 Makefile.inc
drwxr-xr-x - pci1x2x
drwxr-xr-x - pci7420
drwxr-xr-x - pcixx12